1 /* $NetBSD: sunxi_ccu.c,v 1.14 2021/11/07 17:13:12 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_soc.h"
30 #include "opt_multiprocessor.h"
31 #include "opt_console.h"
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: sunxi_ccu.c,v 1.14 2021/11/07 17:13:12 jmcneill Exp $");
35
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/cpu.h>
39 #include <sys/device.h>
40
41 #include <dev/fdt/fdtvar.h>
42
43 #include <dev/clk/clk_backend.h>
44
45 #include <arm/sunxi/sunxi_ccu.h>
46
47 static void *
sunxi_ccu_reset_acquire(device_t dev,const void * data,size_t len)48 sunxi_ccu_reset_acquire(device_t dev, const void *data, size_t len)
49 {
50 struct sunxi_ccu_softc * const sc = device_private(dev);
51 struct sunxi_ccu_reset *reset;
52
53 if (len != 4)
54 return NULL;
55
56 const u_int reset_id = be32dec(data);
57
58 if (reset_id >= sc->sc_nresets)
59 return NULL;
60
61 reset = &sc->sc_resets[reset_id];
62 if (reset->mask == 0)
63 return NULL;
64
65 return reset;
66 }
67
68 static void
sunxi_ccu_reset_release(device_t dev,void * priv)69 sunxi_ccu_reset_release(device_t dev, void *priv)
70 {
71 }
72
73 static int
sunxi_ccu_reset_assert(device_t dev,void * priv)74 sunxi_ccu_reset_assert(device_t dev, void *priv)
75 {
76 struct sunxi_ccu_softc * const sc = device_private(dev);
77 struct sunxi_ccu_reset * const reset = priv;
78
79 const uint32_t val = CCU_READ(sc, reset->reg);
80 CCU_WRITE(sc, reset->reg, val & ~reset->mask);
81
82 return 0;
83 }
84
85 static int
sunxi_ccu_reset_deassert(device_t dev,void * priv)86 sunxi_ccu_reset_deassert(device_t dev, void *priv)
87 {
88 struct sunxi_ccu_softc * const sc = device_private(dev);
89 struct sunxi_ccu_reset * const reset = priv;
90
91 const uint32_t val = CCU_READ(sc, reset->reg);
92 CCU_WRITE(sc, reset->reg, val | reset->mask);
93
94 return 0;
95 }
96
97 static const struct fdtbus_reset_controller_func sunxi_ccu_fdtreset_funcs = {
98 .acquire = sunxi_ccu_reset_acquire,
99 .release = sunxi_ccu_reset_release,
100 .reset_assert = sunxi_ccu_reset_assert,
101 .reset_deassert = sunxi_ccu_reset_deassert,
102 };
103
104 static struct clk *
sunxi_ccu_clock_decode(device_t dev,int cc_phandle,const void * data,size_t len)105 sunxi_ccu_clock_decode(device_t dev, int cc_phandle, const void *data,
106 size_t len)
107 {
108 struct sunxi_ccu_softc * const sc = device_private(dev);
109 struct sunxi_ccu_clk *clk;
110
111 if (len != 4)
112 return NULL;
113
114 const u_int clock_id = be32dec(data);
115 if (clock_id >= sc->sc_nclks)
116 return NULL;
117
118 clk = &sc->sc_clks[clock_id];
119 if (clk->type == SUNXI_CCU_UNKNOWN)
120 return NULL;
121
122 return &clk->base;
123 }
124
125 static const struct fdtbus_clock_controller_func sunxi_ccu_fdtclock_funcs = {
126 .decode = sunxi_ccu_clock_decode,
127 };
128
129 static struct clk *
sunxi_ccu_clock_get(void * priv,const char * name)130 sunxi_ccu_clock_get(void *priv, const char *name)
131 {
132 struct sunxi_ccu_softc * const sc = priv;
133 struct sunxi_ccu_clk *clk;
134
135 clk = sunxi_ccu_clock_find(sc, name);
136 if (clk == NULL)
137 return NULL;
138
139 return &clk->base;
140 }
141
142 static void
sunxi_ccu_clock_put(void * priv,struct clk * clk)143 sunxi_ccu_clock_put(void *priv, struct clk *clk)
144 {
145 }
146
147 static u_int
sunxi_ccu_clock_get_rate(void * priv,struct clk * clkp)148 sunxi_ccu_clock_get_rate(void *priv, struct clk *clkp)
149 {
150 struct sunxi_ccu_softc * const sc = priv;
151 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
152 struct clk *clkp_parent;
153
154 if (clk->get_rate)
155 return clk->get_rate(sc, clk);
156
157 clkp_parent = clk_get_parent(clkp);
158 if (clkp_parent == NULL) {
159 aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
160 return 0;
161 }
162
163 return clk_get_rate(clkp_parent);
164 }
165
166 static int
sunxi_ccu_clock_set_rate(void * priv,struct clk * clkp,u_int rate)167 sunxi_ccu_clock_set_rate(void *priv, struct clk *clkp, u_int rate)
168 {
169 struct sunxi_ccu_softc * const sc = priv;
170 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
171 struct clk *clkp_parent;
172
173 if (clkp->flags & CLK_SET_RATE_PARENT) {
174 clkp_parent = clk_get_parent(clkp);
175 if (clkp_parent == NULL) {
176 aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
177 return ENXIO;
178 }
179 return clk_set_rate(clkp_parent, rate);
180 }
181
182 if (clk->set_rate)
183 return clk->set_rate(sc, clk, rate);
184
185 return ENXIO;
186 }
187
188 static u_int
sunxi_ccu_clock_round_rate(void * priv,struct clk * clkp,u_int rate)189 sunxi_ccu_clock_round_rate(void *priv, struct clk *clkp, u_int rate)
190 {
191 struct sunxi_ccu_softc * const sc = priv;
192 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
193 struct clk *clkp_parent;
194
195 if (clkp->flags & CLK_SET_RATE_PARENT) {
196 clkp_parent = clk_get_parent(clkp);
197 if (clkp_parent == NULL) {
198 aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
199 return 0;
200 }
201 return clk_round_rate(clkp_parent, rate);
202 }
203
204 if (clk->round_rate)
205 return clk->round_rate(sc, clk, rate);
206
207 return 0;
208 }
209
210 static int
sunxi_ccu_clock_enable(void * priv,struct clk * clkp)211 sunxi_ccu_clock_enable(void *priv, struct clk *clkp)
212 {
213 struct sunxi_ccu_softc * const sc = priv;
214 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
215 struct clk *clkp_parent;
216 int error = 0;
217
218 clkp_parent = clk_get_parent(clkp);
219 if (clkp_parent != NULL) {
220 error = clk_enable(clkp_parent);
221 if (error != 0)
222 return error;
223 }
224
225 if (clk->enable)
226 error = clk->enable(sc, clk, 1);
227
228 return error;
229 }
230
231 static int
sunxi_ccu_clock_disable(void * priv,struct clk * clkp)232 sunxi_ccu_clock_disable(void *priv, struct clk *clkp)
233 {
234 struct sunxi_ccu_softc * const sc = priv;
235 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
236 int error = EINVAL;
237
238 if (clk->enable)
239 error = clk->enable(sc, clk, 0);
240
241 return error;
242 }
243
244 static int
sunxi_ccu_clock_set_parent(void * priv,struct clk * clkp,struct clk * clkp_parent)245 sunxi_ccu_clock_set_parent(void *priv, struct clk *clkp,
246 struct clk *clkp_parent)
247 {
248 struct sunxi_ccu_softc * const sc = priv;
249 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
250
251 if (clk->set_parent == NULL)
252 return EINVAL;
253
254 return clk->set_parent(sc, clk, clkp_parent->name);
255 }
256
257 static struct clk *
sunxi_ccu_clock_get_parent(void * priv,struct clk * clkp)258 sunxi_ccu_clock_get_parent(void *priv, struct clk *clkp)
259 {
260 struct sunxi_ccu_softc * const sc = priv;
261 struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
262 struct sunxi_ccu_clk *clk_parent;
263 const char *parent;
264
265 if (clk->get_parent == NULL)
266 return NULL;
267
268 parent = clk->get_parent(sc, clk);
269 if (parent == NULL)
270 return NULL;
271
272 clk_parent = sunxi_ccu_clock_find(sc, parent);
273 if (clk_parent != NULL)
274 return &clk_parent->base;
275
276 /* No parent in this domain, try FDT */
277 return fdtbus_clock_get(sc->sc_phandle, parent);
278 }
279
280 static const struct clk_funcs sunxi_ccu_clock_funcs = {
281 .get = sunxi_ccu_clock_get,
282 .put = sunxi_ccu_clock_put,
283 .get_rate = sunxi_ccu_clock_get_rate,
284 .set_rate = sunxi_ccu_clock_set_rate,
285 .round_rate = sunxi_ccu_clock_round_rate,
286 .enable = sunxi_ccu_clock_enable,
287 .disable = sunxi_ccu_clock_disable,
288 .set_parent = sunxi_ccu_clock_set_parent,
289 .get_parent = sunxi_ccu_clock_get_parent,
290 };
291
292 struct sunxi_ccu_clk *
sunxi_ccu_clock_find(struct sunxi_ccu_softc * sc,const char * name)293 sunxi_ccu_clock_find(struct sunxi_ccu_softc *sc, const char *name)
294 {
295 for (int i = 0; i < sc->sc_nclks; i++) {
296 if (sc->sc_clks[i].base.name == NULL)
297 continue;
298 if (strcmp(sc->sc_clks[i].base.name, name) == 0)
299 return &sc->sc_clks[i];
300 }
301
302 return NULL;
303 }
304
305 int
sunxi_ccu_attach(struct sunxi_ccu_softc * sc)306 sunxi_ccu_attach(struct sunxi_ccu_softc *sc)
307 {
308 bus_addr_t addr;
309 bus_size_t size;
310 int i;
311
312 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr, &size) != 0) {
313 aprint_error(": couldn't get registers\n");
314 return ENXIO;
315 }
316 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
317 aprint_error(": couldn't map registers\n");
318 return ENXIO;
319 }
320
321 sc->sc_clkdom.name = device_xname(sc->sc_dev);
322 sc->sc_clkdom.funcs = &sunxi_ccu_clock_funcs;
323 sc->sc_clkdom.priv = sc;
324 for (i = 0; i < sc->sc_nclks; i++) {
325 sc->sc_clks[i].base.domain = &sc->sc_clkdom;
326 clk_attach(&sc->sc_clks[i].base);
327 }
328
329 fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle,
330 &sunxi_ccu_fdtclock_funcs);
331
332 fdtbus_register_reset_controller(sc->sc_dev, sc->sc_phandle,
333 &sunxi_ccu_fdtreset_funcs);
334
335 return 0;
336 }
337
338 void
sunxi_ccu_print(struct sunxi_ccu_softc * sc)339 sunxi_ccu_print(struct sunxi_ccu_softc *sc)
340 {
341 struct sunxi_ccu_clk *clk;
342 struct clk *clkp_parent;
343 const char *type;
344 int i;
345
346 for (i = 0; i < sc->sc_nclks; i++) {
347 clk = &sc->sc_clks[i];
348 if (clk->type == SUNXI_CCU_UNKNOWN)
349 continue;
350
351 clkp_parent = clk_get_parent(&clk->base);
352
353 switch (clk->type) {
354 case SUNXI_CCU_GATE: type = "gate"; break;
355 case SUNXI_CCU_NM: type = "nm"; break;
356 case SUNXI_CCU_NKMP: type = "nkmp"; break;
357 case SUNXI_CCU_PREDIV: type = "prediv"; break;
358 case SUNXI_CCU_DIV: type = "div"; break;
359 case SUNXI_CCU_PHASE: type = "phase"; break;
360 case SUNXI_CCU_FIXED_FACTOR: type = "fixed-factor"; break;
361 case SUNXI_CCU_FRACTIONAL: type = "fractional"; break;
362 case SUNXI_CCU_MUX: type = "mux"; break;
363 default: type = "???"; break;
364 }
365
366 aprint_debug_dev(sc->sc_dev,
367 "%3d %-12s %2s %-12s %-7s ",
368 i,
369 clk->base.name,
370 clkp_parent ? "<-" : "",
371 clkp_parent ? clkp_parent->name : "",
372 type);
373 aprint_debug("%10u Hz\n", clk_get_rate(&clk->base));
374 }
375 }
376