1 /* $NetBSD: sun8i_v3s_ccu.h,v 1.1 2021/05/05 10:24:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Rui-Xiang Guo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __CCU_V3S_H__ 30 #define __CCU_V3S_H__ 31 32 #define V3S_CLK_PLL_CPU 0 33 #define V3S_CLK_PLL_AUDIO_BASE 1 34 #define V3S_CLK_PLL_AUDIO 2 35 #define V3S_CLK_PLL_AUDIO_2X 3 36 #define V3S_CLK_PLL_AUDIO_4X 4 37 #define V3S_CLK_PLL_AUDIO_8X 5 38 #define V3S_CLK_PLL_VIDEO 6 39 #define V3S_CLK_PLL_VE 7 40 #define V3S_CLK_PLL_DDR 8 41 #define V3S_CLK_PLL_PERIPH0 9 42 #define V3S_CLK_PLL_PERIPH0_2X 10 43 #define V3S_CLK_PLL_ISP 11 44 #define V3S_CLK_PLL_PERIPH1 12 45 #define V3S_CLK_CPU 14 46 #define V3S_CLK_AXI 15 47 #define V3S_CLK_AHB1 16 48 #define V3S_CLK_APB1 17 49 #define V3S_CLK_APB2 18 50 #define V3S_CLK_AHB2 19 51 #define V3S_CLK_BUS_CE 20 52 #define V3S_CLK_BUS_DMA 21 53 #define V3S_CLK_BUS_MMC0 22 54 #define V3S_CLK_BUS_MMC1 23 55 #define V3S_CLK_BUS_MMC2 24 56 #define V3S_CLK_BUS_DRAM 25 57 #define V3S_CLK_BUS_EMAC 26 58 #define V3S_CLK_BUS_HSTIMER 27 59 #define V3S_CLK_BUS_SPI 28 60 #define V3S_CLK_BUS_OTG 29 61 #define V3S_CLK_BUS_EHCI 30 62 #define V3S_CLK_BUS_OHCI 31 63 #define V3S_CLK_BUS_VE 32 64 #define V3S_CLK_BUS_TCON 33 65 #define V3S_CLK_BUS_CSI 34 66 #define V3S_CLK_BUS_DE 35 67 #define V3S_CLK_BUS_CODEC 36 68 #define V3S_CLK_BUS_PIO 37 69 #define V3S_CLK_BUS_I2C0 38 70 #define V3S_CLK_BUS_I2C1 39 71 #define V3S_CLK_BUS_UART0 40 72 #define V3S_CLK_BUS_UART1 41 73 #define V3S_CLK_BUS_UART2 42 74 #define V3S_CLK_BUS_EPHY 43 75 #define V3S_CLK_BUS_DBG 44 76 #define V3S_CLK_MMC0 45 77 #define V3S_CLK_MMC0_SAMPLE 46 78 #define V3S_CLK_MMC0_OUTPUT 47 79 #define V3S_CLK_MMC1 48 80 #define V3S_CLK_MMC1_SAMPLE 49 81 #define V3S_CLK_MMC1_OUTPUT 50 82 #define V3S_CLK_MMC2 51 83 #define V3S_CLK_MMC2_SAMPLE 52 84 #define V3S_CLK_MMC2_OUTPUT 53 85 #define V3S_CLK_CE 54 86 #define V3S_CLK_SPI 55 87 #define V3S_CLK_USBPHY 56 88 #define V3S_CLK_USBOHCI 57 89 #define V3S_CLK_DRAM 58 90 #define V3S_CLK_DRAM_VE 59 91 #define V3S_CLK_DRAM_CSI 60 92 #define V3S_CLK_DRAM_EHCI 61 93 #define V3S_CLK_DRAM_OHCI 62 94 #define V3S_CLK_DE 63 95 #define V3S_CLK_TCON 64 96 #define V3S_CLK_CSI_MISC 65 97 #define V3S_CLK_CSI0_MCLK 66 98 #define V3S_CLK_CSI1_SCLK 67 99 #define V3S_CLK_CSI1_MCLK 68 100 #define V3S_CLK_VE 69 101 #define V3S_CLK_AC_DIG 70 102 #define V3S_CLK_AVS 71 103 #define V3S_CLK_MBUS 72 104 #define V3S_CLK_MIPI_CSI 73 105 106 #define V3S_RST_USBPHY 0 107 #define V3S_RST_MBUS 1 108 #define V3S_RST_BUS_CE 5 109 #define V3S_RST_BUS_DMA 6 110 #define V3S_RST_BUS_MMC0 7 111 #define V3S_RST_BUS_MMC1 8 112 #define V3S_RST_BUS_MMC2 9 113 #define V3S_RST_BUS_DRAM 11 114 #define V3S_RST_BUS_EMAC 12 115 #define V3S_RST_BUS_HSTIMER 14 116 #define V3S_RST_BUS_SPI 15 117 #define V3S_RST_BUS_OTG 17 118 #define V3S_RST_BUS_EHCI 18 119 #define V3S_RST_BUS_OHCI 22 120 #define V3S_RST_BUS_VE 26 121 #define V3S_RST_BUS_TCON 27 122 #define V3S_RST_BUS_CSI 30 123 #define V3S_RST_BUS_DE 34 124 #define V3S_RST_BUS_DBG 38 125 #define V3S_RST_BUS_EPHY 39 126 #define V3S_RST_BUS_CODEC 40 127 #define V3S_RST_BUS_I2C0 46 128 #define V3S_RST_BUS_I2C1 47 129 #define V3S_RST_BUS_UART0 49 130 #define V3S_RST_BUS_UART1 50 131 #define V3S_RST_BUS_UART2 51 132 133 #endif /* __CCU_V3S_H__ */ 134