1 /* $NetBSD: sun8i_h3_ccu.c,v 1.18 2021/04/24 13:01:35 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31
32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.18 2021/04/24 13:01:35 riastradh Exp $");
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/systm.h>
38
39 #include <dev/fdt/fdtvar.h>
40
41 #include <arm/sunxi/sunxi_ccu.h>
42 #include <arm/sunxi/sun8i_h3_ccu.h>
43
44 #define PLL_CPUX_CTRL_REG 0x000
45 #define PLL_AUDIO_CTRL_REG 0x008
46 #define PLL_VIDEO_CTRL_REG 0x010
47 #define PLL_PERIPH0_CTRL_REG 0x028
48 #define PLL_DE_CTRL_REG 0x048
49 #define AHB1_APB1_CFG_REG 0x054
50 #define APB2_CFG_REG 0x058
51 #define AHB2_CFG_REG 0x05c
52 #define AHB2_CLK_CFG __BITS(1,0)
53 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1
54 #define BUS_CLK_GATING_REG0 0x060
55 #define BUS_CLK_GATING_REG1 0x064
56 #define BUS_CLK_GATING_REG2 0x068
57 #define BUS_CLK_GATING_REG3 0x06c
58 #define BUS_CLK_GATING_REG4 0x070
59 #define THS_CLK_REG 0x074
60 #define SDMMC0_CLK_REG 0x088
61 #define SDMMC1_CLK_REG 0x08c
62 #define SDMMC2_CLK_REG 0x090
63 #define CE_CLK_REG 0x09c
64 #define SPI0_CLK_REG 0x0a0
65 #define SPI1_CLK_REG 0x0a4
66 #define USBPHY_CFG_REG 0x0cc
67 #define MBUS_RST_REG 0x0fc
68 #define DE_CLK_REG 0x104
69 #define TCON0_CLK_REG 0x118
70 #define AC_DIG_CLK_REG 0x140
71 #define HDMI_CLK_REG 0x150
72 #define HDMI_SLOW_CLK_REG 0x154
73 #define BUS_SOFT_RST_REG0 0x2c0
74 #define BUS_SOFT_RST_REG1 0x2c4
75 #define BUS_SOFT_RST_REG2 0x2c8
76 #define BUS_SOFT_RST_REG3 0x2d0
77 #define BUS_SOFT_RST_REG4 0x2d8
78
79 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *);
80 static void sun8i_h3_ccu_attach(device_t, device_t, void *);
81
82 static const struct device_compatible_entry compat_data[] = {
83 { .compat = "allwinner,sun8i-h3-ccu" },
84 { .compat = "allwinner,sun50i-h5-ccu" },
85 DEVICE_COMPAT_EOL
86 };
87
88 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc),
89 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL);
90
91 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = {
92 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0),
93 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1),
94 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2),
95 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3),
96
97 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31),
98
99 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
100 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
101 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
102 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
103 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
104 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
105 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
106 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
107 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
108 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
109 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
110 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
111 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
112 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
113 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
114 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26),
115 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27),
116 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28),
117 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29),
118 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30),
119 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31),
120
121 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
122 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
123 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
124 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5),
125 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
126 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9),
127 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
128 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
129 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
130 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
131 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
132 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
133 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
134
135 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
136
137 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
138 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
139 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8),
140 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
141 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
142 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
143
144 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
145 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
146 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
147 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
148 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
149 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
150 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
151 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20),
152 };
153
154 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
155 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
156 static const char *apb1_parents[] = { "ahb1" };
157 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
158 static const char *ce_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" };
159 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
160 static const char *ths_parents[] = { "hosc" };
161 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
162 static const char *hdmi_parents[] = { "pll_video" };
163 static const char *tcon0_parents[] = { "pll_video" };
164
165 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_cpux_table[] = {
166 { 60000000, 9, 0, 0, 2 },
167 { 66000000, 10, 0, 0, 2 },
168 { 72000000, 11, 0, 0, 2 },
169 { 78000000, 12, 0, 0, 2 },
170 { 84000000, 13, 0, 0, 2 },
171 { 90000000, 14, 0, 0, 2 },
172 { 96000000, 15, 0, 0, 2 },
173 { 102000000, 16, 0, 0, 2 },
174 { 108000000, 17, 0, 0, 2 },
175 { 114000000, 18, 0, 0, 2 },
176 { 120000000, 9, 0, 0, 1 },
177 { 132000000, 10, 0, 0, 1 },
178 { 144000000, 11, 0, 0, 1 },
179 { 156000000, 12, 0, 0, 1 },
180 { 168000000, 13, 0, 0, 1 },
181 { 180000000, 14, 0, 0, 1 },
182 { 192000000, 15, 0, 0, 1 },
183 { 204000000, 16, 0, 0, 1 },
184 { 216000000, 17, 0, 0, 1 },
185 { 228000000, 18, 0, 0, 1 },
186 { 240000000, 9, 0, 0, 0 },
187 { 264000000, 10, 0, 0, 0 },
188 { 288000000, 11, 0, 0, 0 },
189 { 312000000, 12, 0, 0, 0 },
190 { 336000000, 13, 0, 0, 0 },
191 { 360000000, 14, 0, 0, 0 },
192 { 384000000, 15, 0, 0, 0 },
193 { 408000000, 16, 0, 0, 0 },
194 { 432000000, 17, 0, 0, 0 },
195 { 456000000, 18, 0, 0, 0 },
196 { 480000000, 19, 0, 0, 0 },
197 { 504000000, 20, 0, 0, 0 },
198 { 528000000, 21, 0, 0, 0 },
199 { 552000000, 22, 0, 0, 0 },
200 { 576000000, 23, 0, 0, 0 },
201 { 600000000, 24, 0, 0, 0 },
202 { 624000000, 25, 0, 0, 0 },
203 { 648000000, 26, 0, 0, 0 },
204 { 672000000, 27, 0, 0, 0 },
205 { 696000000, 28, 0, 0, 0 },
206 { 720000000, 29, 0, 0, 0 },
207 { 768000000, 15, 1, 0, 0 },
208 { 792000000, 10, 2, 0, 0 },
209 { 816000000, 16, 1, 0, 0 },
210 { 864000000, 17, 1, 0, 0 },
211 { 912000000, 18, 1, 0, 0 },
212 { 936000000, 12, 2, 0, 0 },
213 { 960000000, 19, 1, 0, 0 },
214 { 1008000000, 20, 1, 0, 0 },
215 { 1056000000, 21, 1, 0, 0 },
216 { 1080000000, 14, 2, 0, 0 },
217 { 1104000000, 22, 1, 0, 0 },
218 { 1152000000, 23, 1, 0, 0 },
219 { 1200000000, 24, 1, 0, 0 },
220 { 1224000000, 16, 2, 0, 0 },
221 { 1248000000, 25, 1, 0, 0 },
222 { 1296000000, 26, 1, 0, 0 },
223 { 1344000000, 27, 1, 0, 0 },
224 { 1368000000, 18, 2, 0, 0 },
225 { 1392000000, 28, 1, 0, 0 },
226 { 1440000000, 29, 1, 0, 0 },
227 { 1512000000, 20, 2, 0, 0 },
228 { 1536000000, 15, 3, 0, 0 },
229 { 1584000000, 21, 2, 0, 0 },
230 { 1632000000, 16, 3, 0, 0 },
231 { 1656000000, 22, 2, 0, 0 },
232 { 1728000000, 23, 2, 0, 0 },
233 { 1800000000, 24, 2, 0, 0 },
234 { 1824000000, 18, 3, 0, 0 },
235 { 1872000000, 25, 2, 0, 0 },
236 { 0 }
237 };
238
239 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_ac_dig_table[] = {
240 { 24576000, 13, 0, 0, 13 },
241 { 0 }
242 };
243
244 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = {
245 SUNXI_CCU_NKMP_TABLE(H3_CLK_CPUX, "pll_cpux", "hosc",
246 PLL_CPUX_CTRL_REG, /* reg */
247 __BITS(12,8), /* n */
248 __BITS(5,4), /* k */
249 __BITS(1,0), /* m */
250 __BITS(17,16), /* p */
251 __BIT(31), /* enable */
252 __BIT(28), /* lock */
253 sun8i_h3_cpux_table, /* table */
254 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2),
255
256 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
257 PLL_PERIPH0_CTRL_REG, /* reg */
258 __BITS(12,8), /* n */
259 __BITS(5,4), /* k */
260 0, /* m */
261 __BITS(17,16), /* p */
262 __BIT(31), /* enable */
263 SUNXI_CCU_NKMP_DIVIDE_BY_TWO),
264
265 SUNXI_CCU_FIXED_FACTOR(H3_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2),
266
267 SUNXI_CCU_FRACTIONAL(H3_CLK_PLL_VIDEO, "pll_video", "hosc",
268 PLL_VIDEO_CTRL_REG, /* reg */
269 __BITS(14,8), /* m */
270 16, /* m_min */
271 50, /* m_max */
272 __BIT(24), /* div_en */
273 __BIT(25), /* frac_sel */
274 270000000, 297000000, /* frac values */
275 __BITS(3,0), /* prediv */
276 4, /* prediv_val */
277 __BIT(31), /* enable */
278 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE),
279
280 SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc",
281 PLL_AUDIO_CTRL_REG, /* reg */
282 __BITS(14,8), /* n */
283 0, /* k */
284 __BITS(4,0), /* m */
285 __BITS(19,16), /* p */
286 __BIT(31), /* enable */
287 __BIT(28), /* lock */
288 sun8i_h3_ac_dig_table, /* table */
289 0),
290
291 SUNXI_CCU_FRACTIONAL(H3_CLK_PLL_DE, "pll_de", "hosc",
292 PLL_DE_CTRL_REG, /* reg */
293 __BITS(14,8), /* m */
294 16, /* m_min */
295 50, /* m_max */
296 __BIT(24), /* div_en */
297 __BIT(25), /* frac_sel */
298 270000000, 297000000, /* frac values */
299 __BITS(3,0), /* prediv */
300 2, /* prediv_val */
301 __BIT(31), /* enable */
302 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE),
303
304 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents,
305 AHB1_APB1_CFG_REG, /* reg */
306 __BITS(7,6), /* prediv */
307 __BIT(3), /* prediv_sel */
308 __BITS(5,4), /* div */
309 __BITS(13,12), /* sel */
310 SUNXI_CCU_PREDIV_POWER_OF_TWO),
311
312 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents,
313 AHB2_CFG_REG, /* reg */
314 0, /* prediv */
315 __BIT(1), /* prediv_sel */
316 0, /* div */
317 __BITS(1,0), /* sel */
318 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
319
320 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents,
321 AHB1_APB1_CFG_REG, /* reg */
322 __BITS(9,8), /* div */
323 0, /* sel */
324 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
325
326 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents,
327 APB2_CFG_REG, /* reg */
328 __BITS(17,16), /* n */
329 __BITS(4,0), /* m */
330 __BITS(25,24), /* sel */
331 0, /* enable */
332 SUNXI_CCU_NM_POWER_OF_TWO),
333
334 SUNXI_CCU_NM(H3_CLK_CE, "ce", ce_parents,
335 CE_CLK_REG, /* reg */
336 __BITS(17,16), /* n */
337 __BITS(3,0), /* m */
338 __BITS(25,24), /* sel */
339 __BIT(31), /* enable */
340 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
341
342 SUNXI_CCU_DIV_GATE(H3_CLK_THS, "ths", ths_parents,
343 THS_CLK_REG, /* reg */
344 __BITS(1,0), /* div */
345 __BITS(25,24), /* sel */
346 __BIT(31), /* enable */
347 SUNXI_CCU_DIV_TIMES_TWO),
348
349 SUNXI_CCU_DIV_GATE(H3_CLK_DE, "de", de_parents,
350 DE_CLK_REG, /* reg */
351 __BITS(3,0), /* div */
352 __BITS(26,24), /* sel */
353 __BIT(31), /* enable */
354 0),
355
356 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents,
357 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
358 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
359 SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0",
360 SDMMC0_CLK_REG, __BITS(22,20)),
361 SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0",
362 SDMMC0_CLK_REG, __BITS(10,8)),
363 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents,
364 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
365 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
366 SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1",
367 SDMMC1_CLK_REG, __BITS(22,20)),
368 SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1",
369 SDMMC1_CLK_REG, __BITS(10,8)),
370 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents,
371 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
372 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
373 SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2",
374 SDMMC2_CLK_REG, __BITS(22,20)),
375 SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2",
376 SDMMC2_CLK_REG, __BITS(10,8)),
377
378 SUNXI_CCU_NM(H3_CLK_SPI0, "spi0", mod_parents,
379 SPI0_CLK_REG, /* reg */
380 __BITS(17,16), /* n */
381 __BITS(3,0), /* m */
382 __BITS(25,24), /* sel */
383 __BIT(31), /* enable */
384 SUNXI_CCU_NM_ROUND_DOWN),
385 SUNXI_CCU_NM(H3_CLK_SPI1, "spi1", mod_parents,
386 SPI1_CLK_REG, /* reg */
387 __BITS(17,16), /* n */
388 __BITS(3,0), /* m */
389 __BITS(25,24), /* sel */
390 __BIT(31), /* enable */
391 SUNXI_CCU_NM_ROUND_DOWN),
392
393 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio",
394 AC_DIG_CLK_REG, 31),
395
396 SUNXI_CCU_DIV_GATE(H3_CLK_HDMI, "hdmi", hdmi_parents,
397 HDMI_CLK_REG, /* reg */
398 __BITS(3,0), /* div */
399 __BITS(25,24), /* sel */
400 __BIT(31), /* enable */
401 0),
402
403 SUNXI_CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
404 HDMI_SLOW_CLK_REG, 31),
405
406 SUNXI_CCU_DIV_GATE(H3_CLK_TCON0, "tcon0", tcon0_parents,
407 TCON0_CLK_REG, /* reg */
408 __BITS(3,0), /* div */
409 __BITS(26,24), /* sel */
410 __BIT(31), /* enable */
411 0),
412
413 SUNXI_CCU_GATE(H3_CLK_BUS_CE, "bus-ce", "ahb1",
414 BUS_CLK_GATING_REG0, 5),
415 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1",
416 BUS_CLK_GATING_REG0, 6),
417 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
418 BUS_CLK_GATING_REG0, 8),
419 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
420 BUS_CLK_GATING_REG0, 9),
421 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
422 BUS_CLK_GATING_REG0, 10),
423 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2",
424 BUS_CLK_GATING_REG0, 17),
425 SUNXI_CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1",
426 BUS_CLK_GATING_REG0, 20),
427 SUNXI_CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1",
428 BUS_CLK_GATING_REG0, 21),
429 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1",
430 BUS_CLK_GATING_REG0, 23),
431 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1",
432 BUS_CLK_GATING_REG0, 24),
433 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2",
434 BUS_CLK_GATING_REG0, 25),
435 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2",
436 BUS_CLK_GATING_REG0, 26),
437 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2",
438 BUS_CLK_GATING_REG0, 27),
439 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1",
440 BUS_CLK_GATING_REG0, 28),
441 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2",
442 BUS_CLK_GATING_REG0, 29),
443 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2",
444 BUS_CLK_GATING_REG0, 30),
445 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2",
446 BUS_CLK_GATING_REG0, 31),
447
448 SUNXI_CCU_GATE(H3_CLK_BUS_GPU, "bus-gpu", "ahb1",
449 BUS_CLK_GATING_REG1, 20),
450 SUNXI_CCU_GATE(H3_CLK_BUS_DE, "bus-de", "ahb1",
451 BUS_CLK_GATING_REG1, 12),
452 SUNXI_CCU_GATE(H3_CLK_BUS_HDMI, "bus-hdmi", "ahb1",
453 BUS_CLK_GATING_REG1, 11),
454 SUNXI_CCU_GATE(H3_CLK_BUS_TVE, "bus-tve", "ahb1",
455 BUS_CLK_GATING_REG1, 9),
456 SUNXI_CCU_GATE(H3_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1",
457 BUS_CLK_GATING_REG1, 5),
458 SUNXI_CCU_GATE(H3_CLK_BUS_TCON1, "bus-tcon1", "ahb1",
459 BUS_CLK_GATING_REG1, 4),
460 SUNXI_CCU_GATE(H3_CLK_BUS_TCON0, "bus-tcon0", "ahb1",
461 BUS_CLK_GATING_REG1, 3),
462
463 SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1",
464 BUS_CLK_GATING_REG2, 0),
465 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1",
466 BUS_CLK_GATING_REG2, 5),
467 SUNXI_CCU_GATE(H3_CLK_BUS_THS, "bus-ths", "apb2",
468 BUS_CLK_GATING_REG2, 8),
469
470 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2",
471 BUS_CLK_GATING_REG3, 0),
472 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2",
473 BUS_CLK_GATING_REG3, 1),
474 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2",
475 BUS_CLK_GATING_REG3, 2),
476 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2",
477 BUS_CLK_GATING_REG3, 16),
478 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2",
479 BUS_CLK_GATING_REG3, 17),
480 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2",
481 BUS_CLK_GATING_REG3, 18),
482 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2",
483 BUS_CLK_GATING_REG3, 19),
484
485 SUNXI_CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1",
486 BUS_CLK_GATING_REG4, 0),
487
488 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc",
489 USBPHY_CFG_REG, 8),
490 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc",
491 USBPHY_CFG_REG, 9),
492 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc",
493 USBPHY_CFG_REG, 10),
494 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc",
495 USBPHY_CFG_REG, 11),
496 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc",
497 USBPHY_CFG_REG, 16),
498 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc",
499 USBPHY_CFG_REG, 17),
500 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc",
501 USBPHY_CFG_REG, 18),
502 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc",
503 USBPHY_CFG_REG, 19),
504 };
505
506 static void
sun8i_h3_ccu_init(struct sunxi_ccu_softc * sc)507 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc)
508 {
509 uint32_t val;
510
511 /* Set AHB2 source to PLL_PERIPH/2 */
512 val = CCU_READ(sc, AHB2_CFG_REG);
513 val &= ~AHB2_CLK_CFG;
514 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG);
515 CCU_WRITE(sc, AHB2_CFG_REG, val);
516 }
517
518 static int
sun8i_h3_ccu_match(device_t parent,cfdata_t cf,void * aux)519 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux)
520 {
521 struct fdt_attach_args * const faa = aux;
522
523 return of_compatible_match(faa->faa_phandle, compat_data);
524 }
525
526 static void
sun8i_h3_ccu_attach(device_t parent,device_t self,void * aux)527 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux)
528 {
529 struct sunxi_ccu_softc * const sc = device_private(self);
530 struct fdt_attach_args * const faa = aux;
531
532 sc->sc_dev = self;
533 sc->sc_phandle = faa->faa_phandle;
534 sc->sc_bst = faa->faa_bst;
535
536 sc->sc_resets = sun8i_h3_ccu_resets;
537 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets);
538
539 sc->sc_clks = sun8i_h3_ccu_clks;
540 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks);
541
542 if (sunxi_ccu_attach(sc) != 0)
543 return;
544
545 aprint_naive("\n");
546 aprint_normal(": H3 CCU\n");
547
548 sun8i_h3_ccu_init(sc);
549
550 sunxi_ccu_print(sc);
551 }
552