xref: /netbsd-src/sys/arch/arm/sunxi/sun8i_a23_apbclk.c (revision 6e54367a22fbc89a1139d033e95bec0c0cf0975b)
1 /* $NetBSD: sun8i_a23_apbclk.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */
2 
3 /*-
4  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sun8i_a23_apbclk.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kmem.h>
36 #include <sys/bus.h>
37 
38 #include <dev/clk/clk_backend.h>
39 
40 #include <dev/fdt/fdtvar.h>
41 
42 #define	APB0_DIV	__BITS(1,0)
43 
44 static int	sun8i_a23_apbclk_match(device_t, cfdata_t, void *);
45 static void	sun8i_a23_apbclk_attach(device_t, device_t, void *);
46 
47 static struct clk *sun8i_a23_apbclk_decode(device_t, int, const void *, size_t);
48 
49 static const struct fdtbus_clock_controller_func sun8i_a23_apbclk_fdt_funcs = {
50 	.decode = sun8i_a23_apbclk_decode
51 };
52 
53 static struct clk *sun8i_a23_apbclk_get(void *, const char *);
54 static void	sun8i_a23_apbclk_put(void *, struct clk *);
55 static int	sun8i_a23_apbclk_set_rate(void *, struct clk *, u_int);
56 static u_int	sun8i_a23_apbclk_get_rate(void *, struct clk *);
57 static struct clk *sun8i_a23_apbclk_get_parent(void *, struct clk *);
58 
59 static const struct clk_funcs sun8i_a23_apbclk_clk_funcs = {
60 	.get = sun8i_a23_apbclk_get,
61 	.put = sun8i_a23_apbclk_put,
62 	.set_rate = sun8i_a23_apbclk_set_rate,
63 	.get_rate = sun8i_a23_apbclk_get_rate,
64 	.get_parent = sun8i_a23_apbclk_get_parent,
65 };
66 
67 struct sun8i_a23_apbclk_softc {
68 	device_t		sc_dev;
69 	int			sc_phandle;
70 	bus_space_tag_t		sc_bst;
71 	bus_space_handle_t	sc_bsh;
72 
73 	struct clk_domain	sc_clkdom;
74 	struct clk		sc_clk;
75 	struct clk		*sc_parent;
76 };
77 
78 #define	RD4(sc, reg)			\
79 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
80 #define	WR4(sc, reg, val)		\
81 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82 
83 CFATTACH_DECL_NEW(sunxi_a23_apbclk, sizeof(struct sun8i_a23_apbclk_softc),
84     sun8i_a23_apbclk_match, sun8i_a23_apbclk_attach, NULL, NULL);
85 
86 static const struct device_compatible_entry compat_data[] = {
87 	{ .compat = "allwinner,sun8i-a23-apb0-clk" },
88 	DEVICE_COMPAT_EOL
89 };
90 
91 static int
sun8i_a23_apbclk_match(device_t parent,cfdata_t cf,void * aux)92 sun8i_a23_apbclk_match(device_t parent, cfdata_t cf, void *aux)
93 {
94 	const struct fdt_attach_args *faa = aux;
95 
96 	return of_compatible_match(faa->faa_phandle, compat_data);
97 }
98 
99 static void
sun8i_a23_apbclk_attach(device_t parent,device_t self,void * aux)100 sun8i_a23_apbclk_attach(device_t parent, device_t self, void *aux)
101 {
102 	struct sun8i_a23_apbclk_softc * const sc = device_private(self);
103 	const struct fdt_attach_args *faa = aux;
104 	const int phandle = faa->faa_phandle;
105 	bus_addr_t addr;
106 	bus_size_t size;
107 
108 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
109 		aprint_error(": couldn't get registers\n");
110 		return;
111 	}
112 
113 	sc->sc_dev = self;
114 	sc->sc_phandle = phandle;
115 	sc->sc_bst = faa->faa_bst;
116 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
117 		aprint_error(": couldn't map registers\n");
118 		return;
119 	}
120 	sc->sc_parent = fdtbus_clock_get_index(phandle, 0);
121 
122 	sc->sc_clkdom.funcs = &sun8i_a23_apbclk_clk_funcs;
123 	sc->sc_clkdom.priv = sc;
124 
125 	sc->sc_clk.domain = &sc->sc_clkdom;
126 	sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
127 
128 	aprint_naive("\n");
129 	aprint_normal(": A23 APB0 clock\n");
130 
131 	fdtbus_register_clock_controller(self, phandle, &sun8i_a23_apbclk_fdt_funcs);
132 }
133 
134 static struct clk *
sun8i_a23_apbclk_decode(device_t dev,int cc_phandle,const void * data,size_t len)135 sun8i_a23_apbclk_decode(device_t dev, int cc_phandle, const void *data,
136 		     size_t len)
137 {
138 	struct sun8i_a23_apbclk_softc * const sc = device_private(dev);
139 
140 	if (len != 0)
141 		return NULL;
142 
143 	return &sc->sc_clk;
144 }
145 
146 static struct clk *
sun8i_a23_apbclk_get(void * priv,const char * name)147 sun8i_a23_apbclk_get(void *priv, const char *name)
148 {
149 	struct sun8i_a23_apbclk_softc * const sc = priv;
150 
151 	if (strcmp(name, sc->sc_clk.name) != 0)
152 		return NULL;
153 
154 	return &sc->sc_clk;
155 }
156 
157 static void
sun8i_a23_apbclk_put(void * priv,struct clk * clk)158 sun8i_a23_apbclk_put(void *priv, struct clk *clk)
159 {
160 }
161 
162 static int
sun8i_a23_apbclk_set_rate(void * priv,struct clk * clk,u_int rate)163 sun8i_a23_apbclk_set_rate(void *priv, struct clk *clk, u_int rate)
164 {
165 	return ENXIO;
166 }
167 
168 static u_int
sun8i_a23_apbclk_get_rate(void * priv,struct clk * clk)169 sun8i_a23_apbclk_get_rate(void *priv, struct clk *clk)
170 {
171 	struct sun8i_a23_apbclk_softc * const sc = priv;
172 	struct clk *clk_parent = clk_get_parent(clk);
173 
174 	const uint32_t val = RD4(sc, 0);
175 	const u_int div = __SHIFTOUT(val, APB0_DIV);
176 
177 	return clk_get_rate(clk_parent) / (div + 1);
178 }
179 
180 static struct clk *
sun8i_a23_apbclk_get_parent(void * priv,struct clk * clk)181 sun8i_a23_apbclk_get_parent(void *priv, struct clk *clk)
182 {
183 	struct sun8i_a23_apbclk_softc * const sc = priv;
184 
185 	return sc->sc_parent;
186 }
187