1 /* $NetBSD: sun6i_dma.c,v 1.3 2017/12/15 02:24:22 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.3 2017/12/15 02:24:22 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/bitops.h> 41 #include <sys/kmem.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define DMA_IRQ_EN_REG0_REG 0x0000 46 #define DMA_IRQ_EN_REG1_REG 0x0004 47 #define DMA_IRQ_EN_REG0_QUEUE_IRQ_EN(n) __BIT(n * 4 + 2) 48 #define DMA_IRQ_EN_REG0_PKG_IRQ_EN(n) __BIT(n * 4 + 1) 49 #define DMA_IRQ_EN_REG0_HLAF_IRQ_EN(n) __BIT(n * 4 + 0) 50 #define DMA_IRQ_EN_REG1_QUEUE_IRQ_EN(n) __BIT((n - 8) * 4 + 2) 51 #define DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1) 52 #define DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0) 53 #define DMA_IRQ_PEND_REG0_REG 0x0010 54 #define DMA_IRQ_PEND_REG1_REG 0x0014 55 #define DMA_IRQ_QUEUE_MASK 0x4444444444444444ULL 56 #define DMA_IRQ_PKG_MASK 0x2222222222222222ULL 57 #define DMA_IRQ_HF_MASK 0x1111111111111111ULL 58 #define DMA_STA_REG 0x0030 59 #define DMA_EN_REG(n) (0x0100 + (n) * 0x40 + 0x00) 60 #define DMA_EN_EN __BIT(0) 61 #define DMA_PAU_REG(n) (0x0100 + (n) * 0x40 + 0x04) 62 #define DMA_PAU_PAUSE __BIT(0) 63 #define DMA_START_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x08) 64 #define DMA_CFG_REG(n) (0x0100 + (n) * 0x40 + 0x0C) 65 #define DMA_CFG_DEST_DATA_WIDTH __BITS(26,25) 66 #define DMA_CFG_DATA_WIDTH(n) ((n) >> 4) 67 #define DMA_CFG_DEST_BST_LEN __BITS(24,23) 68 #define DMA_CFG_BST_LEN(n) ((n) == 1 ? 0 : (((n) >> 3) + 1)) 69 #define DMA_CFG_DEST_ADDR_MODE __BITS(22,21) 70 #define DMA_CFG_ADDR_MODE_LINEAR 0 71 #define DMA_CFG_ADDR_MODE_IO 1 72 #define DMA_CFG_DEST_DRQ_TYPE __BITS(20,16) 73 #define DMA_CFG_DRQ_TYPE_SDRAM 1 74 #define DMA_CFG_SRC_DATA_WIDTH __BITS(10,9) 75 #define DMA_CFG_SRC_BST_LEN __BITS(8,7) 76 #define DMA_CFG_SRC_ADDR_MODE __BITS(6,5) 77 #define DMA_CFG_SRC_DRQ_TYPE __BITS(4,0) 78 #define DMA_CUR_SRC_REG(n) (0x0100 + (n) * 0x40 + 0x10) 79 #define DMA_CUR_DEST_REG(n) (0x0100 + (n) * 0x40 + 0x14) 80 #define DMA_BCNT_LEFT_REG(n) (0x0100 + (n) * 0x40 + 0x18) 81 #define DMA_PARA_REG(n) (0x0100 + (n) * 0x40 + 0x1C) 82 #define DMA_PARA_DATA_BLK_SIZE __BITS(15,8) 83 #define DMA_PARA_WAIT_CYC __BITS(7,0) 84 85 struct sun6idma_desc { 86 uint32_t dma_config; 87 uint32_t dma_srcaddr; 88 uint32_t dma_dstaddr; 89 uint32_t dma_bcnt; 90 uint32_t dma_para; 91 uint32_t dma_next; 92 #define DMA_NULL 0xfffff800 93 }; 94 95 static const struct of_compat_data compat_data[] = { 96 { "allwinner,sun6i-a31-dma", 16 }, 97 { "allwinner,sun8i-a83t-dma", 8 }, 98 { "allwinner,sun8i-h3-dma", 12 }, 99 { "allwinner,sun50i-a64-dma", 8 }, 100 { NULL } 101 }; 102 103 struct sun6idma_channel { 104 uint8_t ch_index; 105 void (*ch_callback)(void *); 106 void *ch_callbackarg; 107 u_int ch_portid; 108 109 bus_dma_segment_t ch_dmasegs[1]; 110 bus_dmamap_t ch_dmamap; 111 void *ch_dmadesc; 112 bus_size_t ch_dmadesclen; 113 }; 114 115 struct sun6idma_softc { 116 device_t sc_dev; 117 bus_space_tag_t sc_bst; 118 bus_space_handle_t sc_bsh; 119 bus_dma_tag_t sc_dmat; 120 int sc_phandle; 121 void *sc_ih; 122 123 kmutex_t sc_lock; 124 125 struct sun6idma_channel *sc_chan; 126 u_int sc_nchan; 127 }; 128 129 #define DMA_READ(sc, reg) \ 130 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 131 #define DMA_WRITE(sc, reg, val) \ 132 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 133 134 static void * 135 sun6idma_acquire(device_t dev, const void *data, size_t len, 136 void (*cb)(void *), void *cbarg) 137 { 138 struct sun6idma_softc *sc = device_private(dev); 139 struct sun6idma_channel *ch = NULL; 140 uint32_t irqen; 141 uint8_t index; 142 143 if (len != 4) 144 return NULL; 145 146 const u_int portid = be32dec(data); 147 if (portid > __SHIFTOUT_MASK(DMA_CFG_SRC_DRQ_TYPE)) 148 return NULL; 149 150 mutex_enter(&sc->sc_lock); 151 152 for (index = 0; index < sc->sc_nchan; index++) { 153 if (sc->sc_chan[index].ch_callback == NULL) { 154 ch = &sc->sc_chan[index]; 155 ch->ch_callback = cb; 156 ch->ch_callbackarg = cbarg; 157 ch->ch_portid = portid; 158 159 irqen = DMA_READ(sc, index < 8 ? 160 DMA_IRQ_EN_REG0_REG : 161 DMA_IRQ_EN_REG1_REG); 162 irqen |= (index < 8 ? 163 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 164 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 165 DMA_WRITE(sc, index < 8 ? 166 DMA_IRQ_EN_REG0_REG : 167 DMA_IRQ_EN_REG1_REG, irqen); 168 169 break; 170 } 171 } 172 173 mutex_exit(&sc->sc_lock); 174 175 return ch; 176 } 177 178 static void 179 sun6idma_release(device_t dev, void *priv) 180 { 181 struct sun6idma_softc *sc = device_private(dev); 182 struct sun6idma_channel *ch = priv; 183 uint32_t irqen; 184 uint8_t index = ch->ch_index; 185 186 mutex_enter(&sc->sc_lock); 187 188 irqen = DMA_READ(sc, index < 8 ? 189 DMA_IRQ_EN_REG0_REG : 190 DMA_IRQ_EN_REG1_REG); 191 irqen &= ~(index < 8 ? 192 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 193 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 194 DMA_WRITE(sc, index < 8 ? 195 DMA_IRQ_EN_REG0_REG : 196 DMA_IRQ_EN_REG1_REG, irqen); 197 198 ch->ch_callback = NULL; 199 ch->ch_callbackarg = NULL; 200 201 mutex_exit(&sc->sc_lock); 202 } 203 204 static int 205 sun6idma_transfer(device_t dev, void *priv, struct fdtbus_dma_req *req) 206 { 207 struct sun6idma_softc *sc = device_private(dev); 208 struct sun6idma_channel *ch = priv; 209 struct sun6idma_desc *desc = ch->ch_dmadesc; 210 uint32_t src, dst, len, cfg, mem_cfg, dev_cfg; 211 uint32_t mem_width, dev_width, mem_burst, dev_burst; 212 213 if (req->dreq_nsegs != 1) 214 return EINVAL; 215 216 mem_width = DMA_CFG_DATA_WIDTH(req->dreq_mem_opt.opt_bus_width); 217 dev_width = DMA_CFG_DATA_WIDTH(req->dreq_dev_opt.opt_bus_width); 218 mem_burst = DMA_CFG_BST_LEN(req->dreq_mem_opt.opt_burst_len); 219 dev_burst = DMA_CFG_BST_LEN(req->dreq_dev_opt.opt_burst_len); 220 221 mem_cfg = __SHIFTIN(mem_width, DMA_CFG_SRC_DATA_WIDTH) | 222 __SHIFTIN(mem_burst, DMA_CFG_SRC_BST_LEN) | 223 __SHIFTIN(DMA_CFG_ADDR_MODE_LINEAR, DMA_CFG_SRC_ADDR_MODE) | 224 __SHIFTIN(DMA_CFG_DRQ_TYPE_SDRAM, DMA_CFG_SRC_DRQ_TYPE); 225 dev_cfg = __SHIFTIN(dev_width, DMA_CFG_SRC_DATA_WIDTH) | 226 __SHIFTIN(dev_burst, DMA_CFG_SRC_BST_LEN) | 227 __SHIFTIN(DMA_CFG_ADDR_MODE_IO, DMA_CFG_SRC_ADDR_MODE) | 228 __SHIFTIN(ch->ch_portid, DMA_CFG_SRC_DRQ_TYPE); 229 230 if (req->dreq_dir == FDT_DMA_READ) { 231 src = req->dreq_dev_phys; 232 dst = req->dreq_segs[0].ds_addr; 233 cfg = mem_cfg << 16 | dev_cfg; 234 } else { 235 src = req->dreq_segs[0].ds_addr; 236 dst = req->dreq_dev_phys; 237 cfg = dev_cfg << 16 | mem_cfg; 238 } 239 len = req->dreq_segs[0].ds_len; 240 241 desc->dma_config = htole32(cfg); 242 desc->dma_srcaddr = htole32(src); 243 desc->dma_dstaddr = htole32(dst); 244 desc->dma_bcnt = htole32(len); 245 desc->dma_para = htole32(0); 246 desc->dma_next = htole32(DMA_NULL); 247 248 bus_dmamap_sync(sc->sc_dmat, ch->ch_dmamap, 0, ch->ch_dmadesclen, 249 BUS_DMASYNC_PREWRITE); 250 251 DMA_WRITE(sc, DMA_START_ADDR_REG(ch->ch_index), 252 ch->ch_dmamap->dm_segs[0].ds_addr); 253 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), DMA_EN_EN); 254 255 if ((DMA_READ(sc, DMA_EN_REG(ch->ch_index)) & DMA_EN_EN) == 0) { 256 aprint_error_dev(sc->sc_dev, 257 "DMA Channel %u failed to start\n", ch->ch_index); 258 return EIO; 259 } 260 261 return 0; 262 } 263 264 static void 265 sun6idma_halt(device_t dev, void *priv) 266 { 267 struct sun6idma_softc *sc = device_private(dev); 268 struct sun6idma_channel *ch = priv; 269 270 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), 0); 271 } 272 273 static const struct fdtbus_dma_controller_func sun6idma_funcs = { 274 .acquire = sun6idma_acquire, 275 .release = sun6idma_release, 276 .transfer = sun6idma_transfer, 277 .halt = sun6idma_halt 278 }; 279 280 static int 281 sun6idma_intr(void *priv) 282 { 283 struct sun6idma_softc *sc = priv; 284 uint32_t pend0, pend1, bit; 285 uint64_t pend, mask; 286 uint8_t index; 287 288 pend0 = DMA_READ(sc, DMA_IRQ_PEND_REG0_REG); 289 pend1 = DMA_READ(sc, DMA_IRQ_PEND_REG1_REG); 290 if (!pend0 && !pend1) 291 return 0; 292 293 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, pend0); 294 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, pend1); 295 296 pend = pend0 | ((uint64_t)pend1 << 32); 297 298 while ((bit = ffs64(pend & DMA_IRQ_PKG_MASK)) != 0) { 299 mask = __BIT(bit - 1); 300 pend &= ~mask; 301 index = (bit - 1) / 4; 302 303 if (sc->sc_chan[index].ch_callback == NULL) 304 continue; 305 sc->sc_chan[index].ch_callback( 306 sc->sc_chan[index].ch_callbackarg); 307 } 308 309 return 1; 310 } 311 312 static int 313 sun6idma_match(device_t parent, cfdata_t cf, void *aux) 314 { 315 struct fdt_attach_args * const faa = aux; 316 317 return of_match_compat_data(faa->faa_phandle, compat_data); 318 } 319 320 static void 321 sun6idma_attach(device_t parent, device_t self, void *aux) 322 { 323 struct sun6idma_softc * const sc = device_private(self); 324 struct fdt_attach_args * const faa = aux; 325 const int phandle = faa->faa_phandle; 326 const size_t desclen = sizeof(struct sun6idma_desc); 327 struct fdtbus_reset *rst; 328 struct clk *clk; 329 char intrstr[128]; 330 bus_addr_t addr; 331 bus_size_t size; 332 int error, nsegs; 333 u_int index; 334 335 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 336 aprint_error(": couldn't get registers\n"); 337 return; 338 } 339 340 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || 341 clk_enable(clk) != 0) { 342 aprint_error(": couldn't enable clock\n"); 343 return; 344 } 345 if ((rst = fdtbus_reset_get_index(phandle, 0)) == NULL || 346 fdtbus_reset_deassert(rst) != 0) { 347 aprint_error(": couldn't de-assert reset\n"); 348 return; 349 } 350 351 sc->sc_dev = self; 352 sc->sc_phandle = phandle; 353 sc->sc_dmat = faa->faa_dmat; 354 sc->sc_bst = faa->faa_bst; 355 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 356 aprint_error(": couldn't map registers\n"); 357 return; 358 } 359 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 360 361 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 362 aprint_error(": failed to decode interrupt\n"); 363 return; 364 } 365 366 sc->sc_nchan = of_search_compatible(phandle, compat_data)->data; 367 sc->sc_chan = kmem_alloc(sizeof(*sc->sc_chan) * sc->sc_nchan, KM_SLEEP); 368 369 aprint_naive("\n"); 370 aprint_normal(": DMA controller (%u channels)\n", sc->sc_nchan); 371 372 DMA_WRITE(sc, DMA_IRQ_EN_REG0_REG, 0); 373 DMA_WRITE(sc, DMA_IRQ_EN_REG1_REG, 0); 374 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, ~0); 375 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, ~0); 376 377 for (index = 0; index < sc->sc_nchan; index++) { 378 struct sun6idma_channel *ch = &sc->sc_chan[index]; 379 ch->ch_index = index; 380 ch->ch_callback = NULL; 381 ch->ch_callbackarg = NULL; 382 ch->ch_dmadesclen = desclen; 383 384 error = bus_dmamem_alloc(sc->sc_dmat, desclen, 0, 0, 385 ch->ch_dmasegs, 1, &nsegs, BUS_DMA_WAITOK); 386 if (error) 387 panic("bus_dmamem_alloc failed: %d", error); 388 error = bus_dmamem_map(sc->sc_dmat, ch->ch_dmasegs, nsegs, 389 desclen, &ch->ch_dmadesc, BUS_DMA_WAITOK); 390 if (error) 391 panic("bus_dmamem_map failed: %d", error); 392 error = bus_dmamap_create(sc->sc_dmat, desclen, 1, desclen, 0, 393 BUS_DMA_WAITOK, &ch->ch_dmamap); 394 if (error) 395 panic("bus_dmamap_create failed: %d", error); 396 error = bus_dmamap_load(sc->sc_dmat, ch->ch_dmamap, 397 ch->ch_dmadesc, desclen, NULL, BUS_DMA_WAITOK); 398 if (error) 399 panic("bus_dmamap_load failed: %d", error); 400 401 DMA_WRITE(sc, DMA_EN_REG(index), 0); 402 } 403 404 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SCHED, FDT_INTR_MPSAFE, 405 sun6idma_intr, sc); 406 if (sc->sc_ih == NULL) { 407 aprint_error_dev(sc->sc_dev, 408 "couldn't establish interrupt on %s\n", intrstr); 409 return; 410 } 411 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 412 413 fdtbus_register_dma_controller(self, phandle, &sun6idma_funcs); 414 } 415 416 CFATTACH_DECL_NEW(sun6i_dma, sizeof(struct sun6idma_softc), 417 sun6idma_match, sun6idma_attach, NULL, NULL); 418 419 #ifdef DDB 420 void sun6idma_dump(void); 421 422 void 423 sun6idma_dump(void) 424 { 425 struct sun6idma_softc *sc; 426 device_t dev; 427 u_int index; 428 429 dev = device_find_by_driver_unit("sun6idma", 0); 430 if (dev == NULL) 431 return; 432 sc = device_private(dev); 433 434 device_printf(dev, "DMA_IRQ_EN_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG0_REG)); 435 device_printf(dev, "DMA_IRQ_EN_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG1_REG)); 436 device_printf(dev, "DMA_IRQ_PEND_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG0_REG)); 437 device_printf(dev, "DMA_IRQ_PEND_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG1_REG)); 438 device_printf(dev, "DMA_STA_REG: %08x\n", DMA_READ(sc, DMA_STA_REG)); 439 440 for (index = 0; index < sc->sc_nchan; index++) { 441 struct sun6idma_channel *ch = &sc->sc_chan[index]; 442 if (ch->ch_callback == NULL) 443 continue; 444 device_printf(dev, " %2d: DMA_EN_REG: %08x\n", index, DMA_READ(sc, DMA_EN_REG(index))); 445 device_printf(dev, " %2d: DMA_PAU_REG: %08x\n", index, DMA_READ(sc, DMA_PAU_REG(index))); 446 device_printf(dev, " %2d: DMA_START_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_START_ADDR_REG(index))); 447 device_printf(dev, " %2d: DMA_CFG_REG: %08x\n", index, DMA_READ(sc, DMA_CFG_REG(index))); 448 device_printf(dev, " %2d: DMA_CUR_SRC_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_SRC_REG(index))); 449 device_printf(dev, " %2d: DMA_CUR_DEST_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_DEST_REG(index))); 450 device_printf(dev, " %2d: DMA_BCNT_LEFT_REG: %08x\n", index, DMA_READ(sc, DMA_BCNT_LEFT_REG(index))); 451 device_printf(dev, " %2d: DMA_PARA_REG: %08x\n", index, DMA_READ(sc, DMA_PARA_REG(index))); 452 } 453 } 454 #endif 455