1 /* $NetBSD: exynos_wdt.c,v 1.12 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "exynos_wdt.h"
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.12 2021/01/27 03:10:19 thorpej Exp $");
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/cpu.h>
40 #include <sys/device.h>
41 #include <sys/wdog.h>
42
43 #include <prop/proplib.h>
44
45 #include <dev/sysmon/sysmonvar.h>
46
47 #include <arm/samsung/exynos_reg.h>
48 #include <arm/samsung/exynos_var.h>
49
50 #include <dev/fdt/fdtvar.h>
51
52 #if NEXYNOS_WDT > 0
53 static int exynos_wdt_match(device_t, cfdata_t, void *);
54 static void exynos_wdt_attach(device_t, device_t, void *);
55
56 struct exynos_wdt_softc {
57 device_t sc_dev;
58 bus_space_tag_t sc_bst;
59 bus_space_handle_t sc_wdog_bsh;
60 struct sysmon_wdog sc_smw;
61 u_int sc_wdog_period;
62 u_int sc_wdog_clock_select;
63 u_int sc_wdog_prescaler;
64 uint32_t sc_freq;
65 uint32_t sc_wdog_wtdat;
66 uint32_t sc_wdog_wtcon;
67 bool sc_wdog_armed;
68 };
69
70 #ifndef EXYNOS_WDT_PERIOD_DEFAULT
71 #define EXYNOS_WDT_PERIOD_DEFAULT 60
72 #endif
73
74 CFATTACH_DECL_NEW(exynos_wdt, sizeof(struct exynos_wdt_softc),
75 exynos_wdt_match, exynos_wdt_attach, NULL, NULL);
76
77 static inline uint32_t
exynos_wdt_wdog_read(struct exynos_wdt_softc * sc,bus_size_t o)78 exynos_wdt_wdog_read(struct exynos_wdt_softc *sc, bus_size_t o)
79 {
80 return bus_space_read_4(sc->sc_bst, sc->sc_wdog_bsh, o);
81 }
82
83 static inline void
exynos_wdt_wdog_write(struct exynos_wdt_softc * sc,bus_size_t o,uint32_t v)84 exynos_wdt_wdog_write(struct exynos_wdt_softc *sc, bus_size_t o, uint32_t v)
85 {
86 bus_space_write_4(sc->sc_bst, sc->sc_wdog_bsh, o, v);
87 }
88
89 static const struct device_compatible_entry compat_data[] = {
90 { .compat = "samsung,exynos5420-wdt" },
91 DEVICE_COMPAT_EOL
92 };
93
94 /* ARGSUSED */
95 static int
exynos_wdt_match(device_t parent,cfdata_t cf,void * aux)96 exynos_wdt_match(device_t parent, cfdata_t cf, void *aux)
97 {
98 struct fdt_attach_args * const faa = aux;
99
100 return of_compatible_match(faa->faa_phandle, compat_data);
101 }
102
103 static int
exynos_wdt_tickle(struct sysmon_wdog * smw)104 exynos_wdt_tickle(struct sysmon_wdog *smw)
105 {
106 struct exynos_wdt_softc * const sc = smw->smw_cookie;
107
108 /*
109 * Cause the WDOG to restart counting.
110 */
111 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
112 aprint_debug_dev(sc->sc_dev, "tickle\n");
113 return 0;
114 }
115
116 static int
exynos_wdt_setmode(struct sysmon_wdog * smw)117 exynos_wdt_setmode(struct sysmon_wdog *smw)
118 {
119 struct exynos_wdt_softc * const sc = smw->smw_cookie;
120
121 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
122 /*
123 * Emit magic sequence to turn off WDOG
124 */
125 sc->sc_wdog_wtcon &= ~(WTCON_ENABLE|WTCON_RESET_ENABLE);
126 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
127 delay(1);
128 aprint_debug_dev(sc->sc_dev, "setmode disable\n");
129 return 0;
130 }
131
132 /*
133 * If no changes, just tickle it and return.
134 */
135 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
136 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1;
137 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE
138 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)
139 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);
140
141 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
142 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat);
143 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
144 aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
145 return 0;
146 }
147
148 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
149 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT;
150 smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT;
151 }
152
153 /*
154 * Make sure we don't overflow the counter.
155 */
156 if (smw->smw_period * sc->sc_freq >= UINT16_MAX) {
157 return EINVAL;
158 }
159
160 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1;
161 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE
162 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)
163 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);
164
165 /*
166 * Have to disable to be able to write WTDAT
167 */
168 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON,
169 sc->sc_wdog_wtcon & ~(WTCON_ENABLE | WTCON_RESET_ENABLE));
170 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat);
171 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat);
172 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon);
173
174 aprint_debug_dev(sc->sc_dev, "setmode enable\n");
175 return 0;
176 }
177
178
179 static void
exynos_wdt_attach(device_t parent,device_t self,void * aux)180 exynos_wdt_attach(device_t parent, device_t self, void *aux)
181 {
182 struct exynos_wdt_softc * const sc = device_private(self);
183 // prop_dictionary_t dict = device_properties(self);
184 struct fdt_attach_args * const faa = aux;
185 bus_addr_t addr;
186 bus_size_t size;
187 int error;
188
189 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
190 aprint_error(": couldn't get registers\n");
191 return;
192 }
193
194 sc->sc_dev = self;
195 sc->sc_bst = faa->faa_bst;
196
197 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_wdog_bsh);
198 if (error) {
199 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
200 return;
201 }
202
203 /*
204 * This runs at the Exynos Pclk.
205 */
206 // prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
207 sc->sc_freq = 12000000; /* MJF: HACK hardwire for now */
208 /* Need to figure out how to get freq from dtb */
209 sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON);
210 sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE)
211 && (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE);
212 if (sc->sc_wdog_armed) {
213 sc->sc_wdog_prescaler =
214 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER);
215 sc->sc_wdog_clock_select =
216 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT);
217 sc->sc_freq /= sc->sc_wdog_prescaler;
218 sc->sc_freq >>= 4 + sc->sc_wdog_clock_select;
219 sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT);
220 sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq;
221 } else {
222 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT;
223 sc->sc_wdog_prescaler = 1;
224 /*
225 * Let's see what clock select we should use.
226 */
227 u_int n = __builtin_ffs(sc->sc_freq) - 1;
228 if (n > 7) {
229 sc->sc_wdog_clock_select = WTCON_CLOCK_SELECT_128;
230 sc->sc_freq >>= 7;
231 } else if (n >= 4) {
232 sc->sc_wdog_clock_select = n - 4;
233 sc->sc_freq >>= n;
234 }
235 /*
236 * Let's hope the timer frequency isn't prime. If it is, find
237 * the highest divisor which gives us the least remainder.
238 */
239 sc->sc_wdog_prescaler = 0;
240 u_int best_remainder = 256;
241 u_int max_period = 2 * EXYNOS_WDT_PERIOD_DEFAULT * sc->sc_freq;
242 for (size_t div = 256; UINT16_MAX > div * max_period; div++) {
243 u_int remainder = sc->sc_freq % div;
244 if (remainder == 0) {
245 sc->sc_wdog_prescaler = div;
246 break;
247 }
248 if (remainder < best_remainder) {
249 sc->sc_wdog_prescaler = div;
250 best_remainder = remainder;
251 }
252 }
253 KASSERT(sc->sc_wdog_prescaler != 0);
254 sc->sc_freq /= sc->sc_wdog_prescaler;
255 }
256
257 /*
258 * Does the config file tell us to turn on the watchdog?
259 */
260 if (device_cfdata(self)->cf_flags & 1)
261 sc->sc_wdog_armed = true;
262
263 aprint_naive("\n");
264 aprint_normal(": Exynos Watchdog Timer, default period is %u seconds%s\n",
265 sc->sc_wdog_period,
266 sc->sc_wdog_armed ? " (armed)" : "");
267
268 sc->sc_smw.smw_name = device_xname(self);
269 sc->sc_smw.smw_cookie = sc;
270 sc->sc_smw.smw_setmode = exynos_wdt_setmode;
271 sc->sc_smw.smw_tickle = exynos_wdt_tickle;
272 sc->sc_smw.smw_period = sc->sc_wdog_period;
273
274 if (sc->sc_wdog_armed) {
275 error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
276 sc->sc_wdog_period);
277 if (error)
278 aprint_error_dev(self,
279 "failed to start kernel tickler: %d\n", error);
280 }
281 }
282 #endif /* NEXYNOS_WDOG > 0 */
283
284 void
exynos_wdt_reset(void)285 exynos_wdt_reset(void)
286 {
287 bus_space_tag_t bst = &armv7_generic_bs_tag;
288 bus_space_handle_t bsh = exynos_wdt_bsh;
289
290 (void) splhigh();
291 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 0);
292 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCNT, 1);
293 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON,
294 WTCON_ENABLE | WTCON_RESET_ENABLE);
295 }
296
297