xref: /netbsd-src/sys/arch/arm/rockchip/rk3588_cru.c (revision 90313c06e62e910bf0d1bb24faa9d17dcefd0ab6)
1 /*	$NetBSD: rk3588_cru.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $	*/
2 
3 /*-
4  * Copyright (c) 2022 Ryo Shimizu
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
17  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk3588_cru.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/device.h>
34 
35 #include <dev/fdt/fdtvar.h>
36 
37 #include <arm/rockchip/rk_cru.h>
38 #include <arm/rockchip/rk3588_cru.h>
39 
40 #define PLL_CON(base, n)	(0x0000 + (base) + (n) * 4)
41 #define MODE_CON(base, n)	(0x0280 + (base) + (n) * 4)
42 #define CLKSEL_CON(base, n)	(0x0300 + (base) + (n) * 4)
43 #define CLKGATE_CON(base, n)	(0x0800 + (base) + (n) * 4)
44 #define SOFTRST_CON(base, n)	(0x0a00 + (base) + (n) * 4)
45 /* base of above *_CON() macro */
46 #define PHP			0x00008000
47 #define PMU			0x00030000
48 #define BIGCORE0		0x00050000
49 #define BIGCORE1		0x00052000
50 #define DSU			0x00058000
51 
52 #define RK3588_PHYREF_ALT_GATE	0x0c38
53 
54 static int rk3588_cru_match(device_t, cfdata_t, void *);
55 static void rk3588_cru_attach(device_t, device_t, void *);
56 
57 static const struct device_compatible_entry compat_data[] = {
58 	{ .compat = "rockchip,rk3588-cru" },
59 	DEVICE_COMPAT_EOL
60 };
61 
62 CFATTACH_DECL_NEW(rk3588_cru, sizeof(struct rk_cru_softc),
63     rk3588_cru_match, rk3588_cru_attach, NULL, NULL);
64 
65 #define RK3588_CLK_CORE_L_SEL_MASK	__BITS(6,5)
66 #define RK3588_CLK_DSU_SEL_DF_MASK	__BIT(15)
67 #define RK3588_CLK_DSU_DF_SRC_MASK	__BITS(6,5)
68 #define RK3588_CLK_DSU_DF_DIV_MASK	__BITS(4,0)
69 #define RK3588_ACLKM_DSU_DIV_MASK	__BITS(5,1)
70 #define RK3588_ACLKS_DSU_DIV_MASK	__BITS(10,6)
71 #define RK3588_ACLKMP_DSU_DIV_MASK	__BITS(15,11)
72 #define RK3588_PERIPH_DSU_DIV_MASK	__BITS(4,0)
73 #define RK3588_ATCLK_DSU_DIV_MASK	__BITS(4,0)
74 #define RK3588_GICCLK_DSU_DIV_MASK	__BITS(9,5)
75 
76 #define RK3588_CORE_L_SEL_CORE(regoff, apllcore)			\
77 	{								\
78 		.reg = CLKSEL_CON(DSU, 6 + (regoff)),			\
79 		.mask = RK3588_CLK_CORE_L_SEL_MASK,			\
80 		.val = __SHIFTIN((apllcore), RK3588_CLK_CORE_L_SEL_MASK)\
81 	}
82 
83 #define RK3588_CORE_L_SEL_DSU(seldsu, divdsu)				\
84 	{								\
85 		.reg = CLKSEL_CON(DSU, 0),				\
86 		.mask =							\
87 		    RK3588_CLK_DSU_DF_SRC_MASK |			\
88 		    RK3588_CLK_DSU_DF_DIV_MASK |			\
89 		    RK3588_CLK_DSU_SEL_DF_MASK,				\
90 		.val =							\
91 		    __SHIFTIN((seldsu), RK3588_CLK_DSU_DF_SRC_MASK) |	\
92 		    __SHIFTIN((divdsu) - 1, RK3588_CLK_DSU_DF_DIV_MASK) |\
93 		    __SHIFTIN(0, RK3588_CLK_DSU_SEL_DF_MASK)		\
94 	}
95 
96 #define RK3588_CORE_L_SEL_ACLKS(aclkm, aclkmp, aclks)			\
97 	{								\
98 		.reg = CLKSEL_CON(DSU, 1),				\
99 		.mask =							\
100 		    RK3588_ACLKM_DSU_DIV_MASK |				\
101 		    RK3588_ACLKMP_DSU_DIV_MASK |			\
102 		    RK3588_ACLKS_DSU_DIV_MASK,				\
103 		.val =							\
104 		    __SHIFTIN((aclkm) - 1, RK3588_ACLKM_DSU_DIV_MASK) |	\
105 		    __SHIFTIN((aclkmp) - 1, RK3588_ACLKMP_DSU_DIV_MASK)|\
106 		    __SHIFTIN((aclks) - 1, RK3588_ACLKS_DSU_DIV_MASK)	\
107 	}
108 
109 #define RK3588_CORE_L_SEL_PERI(periph)					\
110 	{								\
111 		.reg = CLKSEL_CON(DSU, 2),				\
112 		.mask = RK3588_PERIPH_DSU_DIV_MASK,			\
113 		.val = __SHIFTIN((periph) - 1, RK3588_PERIPH_DSU_DIV_MASK)\
114 	}
115 
116 #define RK3588_CORE_L_SEL_GIC_ATCLK(gicclk, atclk)			\
117 	{								\
118 		.reg = CLKSEL_CON(DSU, 3),				\
119 		.mask =							\
120 		    RK3588_GICCLK_DSU_DIV_MASK |			\
121 		    RK3588_ATCLK_DSU_DIV_MASK,				\
122 		.val =							\
123 		    __SHIFTIN((gicclk) - 1, RK3588_GICCLK_DSU_DIV_MASK) |\
124 		    __SHIFTIN((atclk) - 1, RK3588_ATCLK_DSU_DIV_MASK)	\
125 	}
126 
127 #define RK3588_ARMCLK_L_RATE(targetrate, apllcore, seldsu, divdsu,	\
128     atclk, gicclk, aclkmp, aclkm, aclks, periph)			\
129 	{								\
130 		.rate = (targetrate),					\
131 		.divs = {						\
132 			RK3588_CORE_L_SEL_DSU((seldsu), (divdsu)),	\
133 			RK3588_CORE_L_SEL_ACLKS((aclkm), (aclkmp), (aclks)),\
134 			RK3588_CORE_L_SEL_PERI((periph)),		\
135 			RK3588_CORE_L_SEL_GIC_ATCLK((gicclk), (atclk)),	\
136 		},							\
137 		.pre_muxs = {						\
138 			RK3588_CORE_L_SEL_CORE(0, 0),			\
139 			RK3588_CORE_L_SEL_CORE(1, 0),			\
140 			RK3588_CORE_L_SEL_DSU(3, 2),			\
141 		},							\
142 		.post_muxs = {						\
143 			RK3588_CORE_L_SEL_CORE(0, (apllcore)),		\
144 			RK3588_CORE_L_SEL_CORE(1, (apllcore)),		\
145 			RK3588_CORE_L_SEL_DSU((seldsu), (divdsu))	\
146 		},							\
147 	}
148 
149 static const struct rk_cru_cpu_rate armclk_l_rates[] = {
150 	RK3588_ARMCLK_L_RATE(2208000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
151 	RK3588_ARMCLK_L_RATE(2184000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
152 	RK3588_ARMCLK_L_RATE(2088000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
153 	RK3588_ARMCLK_L_RATE(2040000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
154 	RK3588_ARMCLK_L_RATE(2016000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
155 	RK3588_ARMCLK_L_RATE(1992000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
156 	RK3588_ARMCLK_L_RATE(1896000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
157 	RK3588_ARMCLK_L_RATE(1800000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
158 	RK3588_ARMCLK_L_RATE(1704000000, 0, 3, 1, 3, 3, 3, 3, 3, 3),
159 	RK3588_ARMCLK_L_RATE(1608000000, 0, 3, 1, 3, 3, 3, 2, 3, 3),
160 	RK3588_ARMCLK_L_RATE(1584000000, 0, 3, 1, 3, 3, 3, 2, 3, 3),
161 	RK3588_ARMCLK_L_RATE(1560000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
162 	RK3588_ARMCLK_L_RATE(1536000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
163 	RK3588_ARMCLK_L_RATE(1512000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
164 	RK3588_ARMCLK_L_RATE(1488000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
165 	RK3588_ARMCLK_L_RATE(1464000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
166 	RK3588_ARMCLK_L_RATE(1440000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
167 	RK3588_ARMCLK_L_RATE(1416000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
168 	RK3588_ARMCLK_L_RATE(1392000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
169 	RK3588_ARMCLK_L_RATE(1368000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
170 	RK3588_ARMCLK_L_RATE(1344000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
171 	RK3588_ARMCLK_L_RATE(1320000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
172 	RK3588_ARMCLK_L_RATE(1296000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
173 	RK3588_ARMCLK_L_RATE(1272000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
174 	RK3588_ARMCLK_L_RATE(1248000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
175 	RK3588_ARMCLK_L_RATE(1224000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
176 	RK3588_ARMCLK_L_RATE(1200000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
177 	RK3588_ARMCLK_L_RATE(1104000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
178 	RK3588_ARMCLK_L_RATE(1008000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
179 	RK3588_ARMCLK_L_RATE( 912000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
180 	RK3588_ARMCLK_L_RATE( 816000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
181 	RK3588_ARMCLK_L_RATE( 696000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
182 	RK3588_ARMCLK_L_RATE( 600000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
183 	RK3588_ARMCLK_L_RATE( 408000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
184 	RK3588_ARMCLK_L_RATE( 312000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
185 	RK3588_ARMCLK_L_RATE( 216000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
186 	RK3588_ARMCLK_L_RATE(  96000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
187 };
188 
189 #define RK3588_CLK_CORE_B_SEL_MASK	__BITS(14,13)
190 #define RK3588_CLK_CORE_B_GPLL_DIV_MASK	__BITS(5,1)
191 
192 #define RK3588_ARMCLK_B_RATE(_rate, _bigcore, _apllcore)		\
193 	{								\
194 		.rate = (_rate),					\
195 		.divs[0] = {						\
196 			.reg = CLKSEL_CON(_bigcore, 0),			\
197 			.mask = RK3588_CLK_CORE_B_SEL_MASK |		\
198 			    RK3588_CLK_CORE_B_GPLL_DIV_MASK,		\
199 			.val = __SHIFTIN((_apllcore),			\
200 			    RK3588_CLK_CORE_B_SEL_MASK) |		\
201 			    __SHIFTIN(0,				\
202 			    RK3588_CLK_CORE_B_GPLL_DIV_MASK)		\
203 		},							\
204 		.divs[1] = {						\
205 			.reg = CLKSEL_CON(_bigcore, 1),			\
206 			.mask = RK3588_CLK_CORE_B_SEL_MASK,		\
207 			.val = __SHIFTIN((_apllcore),			\
208 			    RK3588_CLK_CORE_B_SEL_MASK)			\
209 		}							\
210 	}
211 
212 static const struct rk_cru_cpu_rate armclk_b01_rates[] = {
213 	RK3588_ARMCLK_B_RATE(2496000000, BIGCORE0, 1),
214 	RK3588_ARMCLK_B_RATE(2400000000, BIGCORE0, 1),
215 	RK3588_ARMCLK_B_RATE(2304000000, BIGCORE0, 1),
216 	RK3588_ARMCLK_B_RATE(2208000000, BIGCORE0, 1),
217 	RK3588_ARMCLK_B_RATE(2184000000, BIGCORE0, 1),
218 	RK3588_ARMCLK_B_RATE(2088000000, BIGCORE0, 1),
219 	RK3588_ARMCLK_B_RATE(2040000000, BIGCORE0, 1),
220 	RK3588_ARMCLK_B_RATE(2016000000, BIGCORE0, 1),
221 	RK3588_ARMCLK_B_RATE(1992000000, BIGCORE0, 1),
222 	RK3588_ARMCLK_B_RATE(1896000000, BIGCORE0, 1),
223 	RK3588_ARMCLK_B_RATE(1800000000, BIGCORE0, 1),
224 	RK3588_ARMCLK_B_RATE(1704000000, BIGCORE0, 0),
225 	RK3588_ARMCLK_B_RATE(1608000000, BIGCORE0, 0),
226 	RK3588_ARMCLK_B_RATE(1584000000, BIGCORE0, 0),
227 	RK3588_ARMCLK_B_RATE(1560000000, BIGCORE0, 0),
228 	RK3588_ARMCLK_B_RATE(1536000000, BIGCORE0, 0),
229 	RK3588_ARMCLK_B_RATE(1512000000, BIGCORE0, 0),
230 	RK3588_ARMCLK_B_RATE(1488000000, BIGCORE0, 0),
231 	RK3588_ARMCLK_B_RATE(1464000000, BIGCORE0, 0),
232 	RK3588_ARMCLK_B_RATE(1440000000, BIGCORE0, 0),
233 	RK3588_ARMCLK_B_RATE(1416000000, BIGCORE0, 0),
234 	RK3588_ARMCLK_B_RATE(1392000000, BIGCORE0, 0),
235 	RK3588_ARMCLK_B_RATE(1368000000, BIGCORE0, 0),
236 	RK3588_ARMCLK_B_RATE(1344000000, BIGCORE0, 0),
237 	RK3588_ARMCLK_B_RATE(1320000000, BIGCORE0, 0),
238 	RK3588_ARMCLK_B_RATE(1296000000, BIGCORE0, 0),
239 	RK3588_ARMCLK_B_RATE(1272000000, BIGCORE0, 0),
240 	RK3588_ARMCLK_B_RATE(1248000000, BIGCORE0, 0),
241 	RK3588_ARMCLK_B_RATE(1224000000, BIGCORE0, 0),
242 	RK3588_ARMCLK_B_RATE(1200000000, BIGCORE0, 0),
243 	RK3588_ARMCLK_B_RATE(1104000000, BIGCORE0, 0),
244 	RK3588_ARMCLK_B_RATE(1008000000, BIGCORE0, 0),
245 	RK3588_ARMCLK_B_RATE( 912000000, BIGCORE0, 0),
246 	RK3588_ARMCLK_B_RATE( 816000000, BIGCORE0, 0),
247 	RK3588_ARMCLK_B_RATE( 696000000, BIGCORE0, 0),
248 	RK3588_ARMCLK_B_RATE( 600000000, BIGCORE0, 0),
249 	RK3588_ARMCLK_B_RATE( 408000000, BIGCORE0, 0),
250 	RK3588_ARMCLK_B_RATE( 312000000, BIGCORE0, 0),
251 	RK3588_ARMCLK_B_RATE( 216000000, BIGCORE0, 0),
252 	RK3588_ARMCLK_B_RATE(  96000000, BIGCORE0, 0),
253 };
254 
255 static const struct rk_cru_cpu_rate armclk_b23_rates[] = {
256 	RK3588_ARMCLK_B_RATE(2496000000, BIGCORE1, 1),
257 	RK3588_ARMCLK_B_RATE(2400000000, BIGCORE1, 1),
258 	RK3588_ARMCLK_B_RATE(2304000000, BIGCORE1, 1),
259 	RK3588_ARMCLK_B_RATE(2208000000, BIGCORE1, 1),
260 	RK3588_ARMCLK_B_RATE(2184000000, BIGCORE1, 1),
261 	RK3588_ARMCLK_B_RATE(2088000000, BIGCORE1, 1),
262 	RK3588_ARMCLK_B_RATE(2040000000, BIGCORE1, 1),
263 	RK3588_ARMCLK_B_RATE(2016000000, BIGCORE1, 1),
264 	RK3588_ARMCLK_B_RATE(1992000000, BIGCORE1, 1),
265 	RK3588_ARMCLK_B_RATE(1896000000, BIGCORE1, 1),
266 	RK3588_ARMCLK_B_RATE(1800000000, BIGCORE1, 1),
267 	RK3588_ARMCLK_B_RATE(1704000000, BIGCORE1, 0),
268 	RK3588_ARMCLK_B_RATE(1608000000, BIGCORE1, 0),
269 	RK3588_ARMCLK_B_RATE(1584000000, BIGCORE1, 0),
270 	RK3588_ARMCLK_B_RATE(1560000000, BIGCORE1, 0),
271 	RK3588_ARMCLK_B_RATE(1536000000, BIGCORE1, 0),
272 	RK3588_ARMCLK_B_RATE(1512000000, BIGCORE1, 0),
273 	RK3588_ARMCLK_B_RATE(1488000000, BIGCORE1, 0),
274 	RK3588_ARMCLK_B_RATE(1464000000, BIGCORE1, 0),
275 	RK3588_ARMCLK_B_RATE(1440000000, BIGCORE1, 0),
276 	RK3588_ARMCLK_B_RATE(1416000000, BIGCORE1, 0),
277 	RK3588_ARMCLK_B_RATE(1392000000, BIGCORE1, 0),
278 	RK3588_ARMCLK_B_RATE(1368000000, BIGCORE1, 0),
279 	RK3588_ARMCLK_B_RATE(1344000000, BIGCORE1, 0),
280 	RK3588_ARMCLK_B_RATE(1320000000, BIGCORE1, 0),
281 	RK3588_ARMCLK_B_RATE(1296000000, BIGCORE1, 0),
282 	RK3588_ARMCLK_B_RATE(1272000000, BIGCORE1, 0),
283 	RK3588_ARMCLK_B_RATE(1248000000, BIGCORE1, 0),
284 	RK3588_ARMCLK_B_RATE(1224000000, BIGCORE1, 0),
285 	RK3588_ARMCLK_B_RATE(1200000000, BIGCORE1, 0),
286 	RK3588_ARMCLK_B_RATE(1104000000, BIGCORE1, 0),
287 	RK3588_ARMCLK_B_RATE(1008000000, BIGCORE1, 0),
288 	RK3588_ARMCLK_B_RATE( 912000000, BIGCORE1, 0),
289 	RK3588_ARMCLK_B_RATE( 816000000, BIGCORE1, 0),
290 	RK3588_ARMCLK_B_RATE( 696000000, BIGCORE1, 0),
291 	RK3588_ARMCLK_B_RATE( 600000000, BIGCORE1, 0),
292 	RK3588_ARMCLK_B_RATE( 408000000, BIGCORE1, 0),
293 	RK3588_ARMCLK_B_RATE( 312000000, BIGCORE1, 0),
294 	RK3588_ARMCLK_B_RATE( 216000000, BIGCORE1, 0),
295 	RK3588_ARMCLK_B_RATE(  96000000, BIGCORE1, 0),
296 };
297 
298 static struct rk_cru_pll_rate rk3588_pll_rates[] = {
299 	RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
300 	RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
301 	RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
302 	RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
303 	RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
304 	RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
305 	RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
306 	RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
307 	RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
308 	RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
309 	RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
310 	RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
311 	RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
312 	RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
313 	RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
314 	RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
315 	RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
316 	RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
317 	RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
318 	RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
319 	RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
320 	RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
321 	RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
322 	RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
323 	RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
324 	RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
325 	RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
326 	RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
327 	RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
328 	RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
329 	RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
330 	RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
331 	RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
332 	RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
333 	RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
334 	RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
335 	RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
336 	RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
337 	RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
338 	RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
339 	RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
340 	RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
341 	RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
342 	RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
343 	RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
344 	RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
345 	RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
346 	RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
347 	RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
348 	RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
349 	RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
350 	RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
351 	RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
352 	RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
353 	RK3588_PLL_RATE( 983040000, 4, 655, 2, 23592),
354 	RK3588_PLL_RATE( 955520000, 3, 477, 2, 49806),
355 	RK3588_PLL_RATE( 903168000, 6, 903, 2, 11009),
356 	RK3588_PLL_RATE( 900000000, 2, 300, 2, 0),
357 	RK3588_PLL_RATE( 850000000, 3, 425, 2, 0),
358 	RK3588_PLL_RATE( 816000000, 2, 272, 2, 0),
359 	RK3588_PLL_RATE( 786432000, 2, 262, 2, 9437),
360 	RK3588_PLL_RATE( 786000000, 1, 131, 2, 0),
361 	RK3588_PLL_RATE( 785560000, 3, 392, 2, 51117),
362 	RK3588_PLL_RATE( 722534400, 8, 963, 2, 24850),
363 	RK3588_PLL_RATE( 600000000, 2, 200, 2, 0),
364 	RK3588_PLL_RATE( 594000000, 2, 198, 2, 0),
365 	RK3588_PLL_RATE( 408000000, 2, 272, 3, 0),
366 	RK3588_PLL_RATE( 312000000, 2, 208, 3, 0),
367 	RK3588_PLL_RATE( 216000000, 2, 288, 4, 0),
368 	RK3588_PLL_RATE( 100000000, 3, 400, 5, 0),
369 	RK3588_PLL_RATE(  96000000, 2, 256, 5, 0),
370 };
371 
372 static const char *mux_pll_parents[] = {
373     "xin24m", "xin32k" };
374 static const char *mux_armclkl_parents[] = {
375     "xin24m", "gpll", "lpll" };
376 static const char *mux_armclkb01_parents[] = {
377     "xin24m", "gpll", "b0pll" };
378 static const char *mux_armclkb23_parents[] = {
379     "xin24m", "gpll", "b1pll" };
380 static const char *b0pll_b1pll_lpll_gpll_parents[]= {
381     "b0pll", "b1pll", "lpll", "gpll" };
382 static const char *gpll_24m_parents[] = {
383     "gpll", "xin24m" };
384 static const char *gpll_aupll_parents[] = {
385     "gpll", "aupll" };
386 static const char *gpll_lpll_parents[] = {
387     "gpll", "lpll" };
388 static const char *gpll_cpll_parents[] = {
389     "gpll", "cpll" };
390 static const char *gpll_spll_parents[] = {
391     "gpll", "spll" };
392 static const char *gpll_cpll_24m_parents[] = {
393     "gpll", "cpll", "xin24m"};
394 static const char *gpll_cpll_aupll_parents[] = {
395     "gpll", "cpll", "aupll"};
396 static const char *gpll_cpll_npll_parents[] = {
397     "gpll", "cpll", "npll"};
398 static const char *gpll_cpll_npll_v0pll_parents[]= {
399     "gpll", "cpll", "npll", "v0pll"};
400 static const char *gpll_cpll_24m_spll_parents[] = {
401     "gpll", "cpll", "xin24m", "spll" };
402 static const char *gpll_cpll_aupll_spll_parents[]= {
403     "gpll", "cpll", "aupll", "spll" };
404 static const char *gpll_cpll_aupll_npll_parents[]= {
405     "gpll", "cpll", "aupll", "npll" };
406 static const char *gpll_cpll_v0pll_aupll_parents[]= {
407     "gpll", "cpll", "v0pll", "aupll" };
408 static const char *gpll_cpll_v0pll_spll_parents[]= {
409     "gpll", "cpll", "v0pll", "spll" };
410 static const char *gpll_cpll_aupll_npll_spll_parents[]= {
411     "gpll", "cpll", "aupll", "npll", "spll" };
412 static const char *gpll_cpll_npll_aupll_spll_parents[]= {
413     "gpll", "cpll", "npll", "aupll", "spll" };
414 static const char *gpll_cpll_dmyaupll_npll_spll_parents[] =
415     { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
416 static const char *gpll_cpll_npll_1000m_parents[]= {
417     "gpll", "cpll", "npll", "clk_1000m_src" };
418 static const char *mux_24m_spll_gpll_cpll_parents[]= {
419     "xin24m", "spll", "gpll", "cpll" };
420 static const char *mux_24m_32k_parents[] = {
421     "xin24m", "xin32k" };
422 static const char *mux_24m_100m_parents[] = {
423     "xin24m", "clk_100m_src" };
424 static const char *mux_200m_100m_parents[] = {
425     "clk_200m_src", "clk_100m_src" };
426 static const char *mux_100m_50m_24m_parents[] = {
427     "clk_100m_src", "clk_50m_src", "xin24m" };
428 static const char *mux_150m_50m_24m_parents[] = {
429     "clk_150m_src", "clk_50m_src", "xin24m" };
430 static const char *mux_150m_100m_24m_parents[] = {
431     "clk_150m_src", "clk_100m_src", "xin24m" };
432 static const char *mux_200m_150m_24m_parents[] = {
433     "clk_200m_src", "clk_150m_src", "xin24m" };
434 static const char *mux_150m_100m_50m_24m_parents[]= {
435     "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
436 static const char *mux_200m_100m_50m_24m_parents[]= {
437     "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
438 static const char *mux_300m_200m_100m_24m_parents[]= {
439     "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
440 static const char *mux_700m_400m_200m_24m_parents[]= {
441     "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin_osc0_func" };
442 static const char *mux_500m_250m_100m_24m_parents[]= {
443     "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin_osc0_func" };
444 static const char *mux_500m_300m_100m_24m_parents[]= {
445     "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin_osc0_func" };
446 static const char *mux_400m_200m_100m_24m_parents[]= {
447     "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin_osc0_func" };
448 static const char *clk_i2s2_2ch_parents[] = {
449     "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" };
450 static const char *clk_i2s3_2ch_parents[] = {
451     "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" };
452 static const char *clk_i2s0_8ch_tx_parents[] = {
453     "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
454 static const char *clk_i2s0_8ch_rx_parents[] = {
455     "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };
456 static const char *clk_i2s1_8ch_tx_parents[] = {
457     "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" };
458 static const char *clk_i2s1_8ch_rx_parents[] = {
459     "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" };
460 static const char *clk_i2s4_8ch_tx_parents[] = {
461     "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" };
462 static const char *clk_i2s5_8ch_tx_parents[] = {
463     "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" };
464 static const char *clk_i2s6_8ch_tx_parents[] = {
465     "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" };
466 static const char *clk_i2s6_8ch_rx_parents[] = {
467     "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" };
468 static const char *clk_i2s7_8ch_rx_parents[] = {
469     "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" };
470 static const char *clk_i2s8_8ch_tx_parents[] = {
471     "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" };
472 static const char *clk_i2s9_8ch_rx_parents[] = {
473     "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" };
474 static const char *clk_i2s10_8ch_rx_parents[] = {
475     "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" };
476 static const char *clk_spdif0_parents[] = {
477     "clk_spdif0_src", "clk_spdif0_frac", "xin12m" };
478 static const char *clk_spdif1_parents[] = {
479     "clk_spdif1_src", "clk_spdif1_frac", "xin12m" };
480 static const char *clk_spdif2_dp0_parents[] = {
481     "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" };
482 static const char *clk_spdif3_parents[] = {
483     "clk_spdif3_src", "clk_spdif3_frac", "xin12m" };
484 static const char *clk_spdif4_parents[] = {
485     "clk_spdif4_src", "clk_spdif4_frac", "xin12m" };
486 static const char *clk_spdif5_dp1_parents[] = {
487     "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" };
488 static const char *clk_uart0_parents[] = {
489     "clk_uart0_src", "clk_uart0_frac", "xin24m" };
490 static const char *clk_uart1_parents[] = {
491     "clk_uart1_src", "clk_uart1_frac", "xin24m" };
492 static const char *clk_uart2_parents[] = {
493     "clk_uart2_src", "clk_uart2_frac", "xin24m" };
494 static const char *clk_uart3_parents[] = {
495     "clk_uart3_src", "clk_uart3_frac", "xin24m" };
496 static const char *clk_uart4_parents[] = {
497     "clk_uart4_src", "clk_uart4_frac", "xin24m" };
498 static const char *clk_uart5_parents[] = {
499     "clk_uart5_src", "clk_uart5_frac", "xin24m" };
500 static const char *clk_uart6_parents[] = {
501     "clk_uart6_src", "clk_uart6_frac", "xin24m" };
502 static const char *clk_uart7_parents[] = {
503     "clk_uart7_src", "clk_uart7_frac", "xin24m" };
504 static const char *clk_uart8_parents[] = {
505     "clk_uart8_src", "clk_uart8_frac", "xin24m" };
506 static const char *clk_uart9_parents[] = {
507     "clk_uart9_src", "clk_uart9_frac", "xin24m" };
508 static const char *clk_gmac0_ptp_ref_parents[] = {
509     "cpll", "clk_gmac0_ptpref_io" };
510 static const char *clk_gmac1_ptp_ref_parents[] = {
511     "cpll", "clk_gmac1_ptpref_io" };
512 static const char *aclk_hdcp1_root_parents[] = {
513     "gpll", "cpll", "clk_hdmitrx_refsrc" };
514 static const char *dclk_vop0_parents[] = {
515     "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
516 static const char *dclk_vop1_parents[] = {
517     "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
518 static const char *dclk_vop2_parents[] = {
519     "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
520 static const char *pmu_200m_100m_parents[] = {
521     "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
522 static const char *pmu_300m_24m_parents[] = {
523     "clk_300m_src", "xin24m" };
524 static const char *pmu_400m_24m_parents[] = {
525     "clk_400m_src", "xin24m" };
526 static const char *pmu_100m_50m_24m_src_parents[]= {
527     "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
528 static const char *pmu_24m_32k_100m_src_parents[]= {
529     "xin24m", "32k", "clk_pmu1_100m_src" };
530 static const char *hclk_pmu1_root_parents[] = {
531     "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
532 static const char *hclk_pmu_cm0_root_parents[] = {
533     "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
534 static const char *mclk_pdm0_parents[] = {
535     "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
536 static const char *mux_24m_ppll_spll_parents[] = {
537     "xin24m", "ppll", "spll" };
538 static const char *mux_24m_ppll_parents[] = {
539     "xin24m", "ppll" };
540 static const char *aclk_vop_sub_src_parents[] = {
541     "aclk_vop_root", "aclk_vop_div2_src" };
542 static const char *clk_ref_pipe_phy0_parents[] = {
543     "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
544 static const char *clk_ref_pipe_phy1_parents[] = {
545     "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
546 static const char *clk_ref_pipe_phy2_parents[] = {
547     "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
548 static const char *i2s0_8ch_mclkout_parents[] = {
549     "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" };
550 static const char *i2s1_8ch_mclkout_parents[] = {
551     "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" };
552 static const char *i2s2_2ch_mclkout_parents[] = {
553     "mclk_i2s2_2ch", "xin12m" };
554 static const char *i2s3_2ch_mclkout_parents[] = {
555     "mclk_i2s3_2ch", "xin12m" };
556 static const char *i2s6_8ch_mclkout_parents[] = {
557     "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" };
558 
559 
560 static struct rk_cru_clk rk3588_cru_clks[] = {
561 	/* PLLs */
562 	RK3588_PLL(RK3588_PLL_B0PLL, "b0pll", mux_pll_parents,
563 	    PLL_CON(BIGCORE0, 0),
564 	    CLKSEL_CON(BIGCORE0, 0),
565 	    __BIT(6),
566 	    __BIT(15),
567 	    rk3588_pll_rates),
568 	RK3588_PLL(RK3588_PLL_B1PLL, "b1pll", mux_pll_parents,
569 	    PLL_CON(BIGCORE1, 8),
570 	    CLKSEL_CON(BIGCORE1, 0),
571 	    __BIT(6),
572 	    __BIT(15),
573 	    rk3588_pll_rates),
574 
575 	RK3588_PLL(RK3588_PLL_LPLL, "lpll", mux_pll_parents,
576 	    PLL_CON(DSU, 16),
577 	    CLKSEL_CON(DSU, 5),
578 	    __BIT(14),
579 	    __BIT(15),
580 	    rk3588_pll_rates),
581 	RK3588_PLL(RK3588_PLL_V0PLL, "v0pll", mux_pll_parents,
582 	    PLL_CON(0, 88),
583 	    MODE_CON(0, 0),
584 	    __BIT(4),
585 	    __BIT(15),
586 	    rk3588_pll_rates),
587 	RK3588_PLL(RK3588_PLL_AUPLL, "aupll", mux_pll_parents,
588 	    PLL_CON(0, 96),
589 	    MODE_CON(0, 0),
590 	    __BIT(6),
591 	    __BIT(15),
592 	    rk3588_pll_rates),
593 	RK3588_PLL(RK3588_PLL_CPLL, "cpll", mux_pll_parents,
594 	    PLL_CON(0, 104),
595 	    MODE_CON(0, 0),
596 	    __BIT(8),
597 	    __BIT(15),
598 	    rk3588_pll_rates),
599 	RK3588_PLL(RK3588_PLL_GPLL, "gpll", mux_pll_parents,
600 	    PLL_CON(0, 112),
601 	    MODE_CON(0, 0),
602 	    __BIT(2),
603 	    __BIT(15),
604 	    rk3588_pll_rates),
605 	RK3588_PLL(RK3588_PLL_NPLL, "npll", mux_pll_parents,
606 	    PLL_CON(0, 120),
607 	    MODE_CON(0, 0),
608 	    __BIT(0),
609 	    __BIT(15),
610 	    rk3588_pll_rates),
611 	RK3588_PLL(RK3588_PLL_PPLL, "ppll", mux_pll_parents,
612 	    PLL_CON(PHP, 128),
613 	    MODE_CON(0, 0),
614 	    __BIT(10),
615 	    __BIT(15),
616 	    rk3588_pll_rates),
617 
618 	/* big,little cores */
619 	RK_CPU_CORE4(RK3588_ARMCLK_L, "armclk_l", mux_armclkl_parents,
620 	    CLKSEL_CON(DSU, 5),		/* mux_reg */
621 	    __BITS(15,14), 2, 1,	/* mux_mask, mux_main, mux_alt */
622 	    CLKSEL_CON(DSU, 6),		/* div0_reg */
623 	    __BITS(4,0),		/* div0_mask */
624 	    CLKSEL_CON(DSU, 6),		/* div1_reg */
625 	    __BITS(11,7),		/* div1_mask */
626 	    CLKSEL_CON(DSU, 7),		/* div2_reg */
627 	    __BITS(4,0),		/* div2_mask */
628 	    CLKSEL_CON(DSU, 7),		/* div3_reg */
629 	    __BITS(11,7),		/* div3_mask */
630 	    armclk_l_rates),
631 	RK_CPU_CORE2(RK3588_ARMCLK_B01, "armclk_b01", mux_armclkb01_parents,
632 	    CLKSEL_CON(BIGCORE0, 0),	/* mux_reg */
633 	    __BITS(7,6), 2, 1,		/* mux_mask, mux_main, mux_alt */
634 	    CLKSEL_CON(BIGCORE0, 0),	/* div0_reg */
635 	    __BITS(12,8),		/* div0_mask */
636 	    CLKSEL_CON(BIGCORE0, 1),	/* div1_reg */
637 	    __BITS(4,0),		/* div1_mask */
638 	    armclk_b01_rates),
639 	RK_CPU_CORE2(RK3588_ARMCLK_B23, "armclk_b23", mux_armclkb23_parents,
640 	    CLKSEL_CON(BIGCORE1, 0),	/* reg */
641 	    __BITS(7,6), 2, 1,		/* mux_mask, mux_main, mux_alt */
642 	    CLKSEL_CON(BIGCORE1, 0),	/* div0_reg */
643 	    __BITS(12,8),		/* div0_mask */
644 	    CLKSEL_CON(BIGCORE1, 1),	/* div1_reg */
645 	    __BITS(4,0),		/* div1_mask */
646 	    armclk_b23_rates),
647 
648 	RK_COMPOSITE_NODIV(RK3588_PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root",
649 	    mux_100m_50m_24m_parents,
650 	    CLKSEL_CON(BIGCORE0, 2), __BITS(1,0),
651 	    CLKGATE_CON(BIGCORE0, 0), __BIT(14),
652 	    0),
653 	RK_GATE(RK3588_PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm",
654 	    "pclk_bigcore0_root",
655 	    CLKGATE_CON(BIGCORE0, 1), 0),
656 	RK_GATE(RK3588_CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m",
657 	    CLKGATE_CON(BIGCORE0, 0), 12),
658 	RK_GATE(RK3588_CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm",
659 	    "armclk_b01",
660 	    CLKGATE_CON(BIGCORE0, 0), 13),
661 
662 	RK_COMPOSITE_NODIV(RK3588_PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root",
663 	    mux_100m_50m_24m_parents,
664 	    CLKSEL_CON(BIGCORE1, 2), __BITS(1,0),
665 	    CLKGATE_CON(BIGCORE1, 0), __BIT(14),
666 	    0),
667 	RK_GATE(RK3588_PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm",
668 	    "pclk_bigcore1_root",
669 	    CLKGATE_CON(BIGCORE1, 1), 0),
670 	RK_GATE(RK3588_CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m",
671 	    CLKGATE_CON(BIGCORE1, 0), 12),
672 	RK_GATE(RK3588_CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm",
673 	    "armclk_b23",
674 	    CLKGATE_CON(BIGCORE1, 0), 13),
675 
676 	RK_COMPOSITE(RK3588_CLK_50M_SRC, "clk_50m_src",
677 	    gpll_cpll_parents,
678 	    CLKSEL_CON(0, 0), __BITS(5,5), __BITS(4,0),
679 	    CLKGATE_CON(0, 0), __BIT(0),
680 	    0),
681 	RK_COMPOSITE(RK3588_CLK_100M_SRC, "clk_100m_src",
682 	    gpll_cpll_parents,
683 	    CLKSEL_CON(0, 0), __BITS(11,11), __BITS(10,6),
684 	    CLKGATE_CON(0, 0), __BIT(1),
685 	    0),
686 	RK_COMPOSITE(RK3588_CLK_150M_SRC, "clk_150m_src",
687 	    gpll_cpll_parents,
688 	    CLKSEL_CON(0, 1), __BITS(5,5), __BITS(4,0),
689 	    CLKGATE_CON(0, 0), __BIT(2),
690 	    0),
691 	RK_COMPOSITE(RK3588_CLK_200M_SRC, "clk_200m_src",
692 	    gpll_cpll_parents,
693 	    CLKSEL_CON(0, 1), __BITS(11,11), __BITS(10,6),
694 	    CLKGATE_CON(0, 0), __BIT(3),
695 	    0),
696 	RK_COMPOSITE(RK3588_CLK_250M_SRC, "clk_250m_src",
697 	    gpll_cpll_parents,
698 	    CLKSEL_CON(0, 2), __BITS(5,5), __BITS(4,0),
699 	    CLKGATE_CON(0, 0), __BIT(4),
700 	    0),
701 	RK_COMPOSITE(RK3588_CLK_300M_SRC, "clk_300m_src",
702 	    gpll_cpll_parents,
703 	    CLKSEL_CON(0, 2), __BITS(11,11), __BITS(10,6),
704 	    CLKGATE_CON(0, 0), __BIT(5),
705 	    0),
706 	RK_COMPOSITE(RK3588_CLK_350M_SRC, "clk_350m_src",
707 	    gpll_spll_parents,
708 	    CLKSEL_CON(0, 3), __BITS(5,5), __BITS(4,0),
709 	    CLKGATE_CON(0, 0), __BIT(6),
710 	    0),
711 	RK_COMPOSITE(RK3588_CLK_400M_SRC, "clk_400m_src",
712 	    gpll_cpll_parents,
713 	    CLKSEL_CON(0, 3), __BITS(11,11), __BITS(10,6),
714 	    CLKGATE_CON(0, 0), __BIT(7),
715 	    0),
716 	RK_COMPOSITE_HALF(RK3588_CLK_450M_SRC, "clk_450m_src",
717 	    gpll_cpll_parents,
718 	    CLKSEL_CON(0, 4), __BITS(5,5),
719 	    __BITS(4,0),
720 	    CLKGATE_CON(0, 0), __BIT(8),
721 	    0),
722 	RK_COMPOSITE(RK3588_CLK_500M_SRC, "clk_500m_src",
723 	    gpll_cpll_parents,
724 	    CLKSEL_CON(0, 4), __BITS(11,11), __BITS(10,6),
725 	    CLKGATE_CON(0, 0), __BIT(9),
726 	    0),
727 	RK_COMPOSITE(RK3588_CLK_600M_SRC, "clk_600m_src",
728 	    gpll_cpll_parents,
729 	    CLKSEL_CON(0, 5), __BITS(5,5), __BITS(4,0),
730 	    CLKGATE_CON(0, 0), __BIT(10),
731 	    0),
732 	RK_COMPOSITE(RK3588_CLK_650M_SRC, "clk_650m_src",
733 	    gpll_lpll_parents,
734 	    CLKSEL_CON(0, 5), __BITS(11,11), __BITS(10,6),
735 	    CLKGATE_CON(0, 0), __BIT(11),
736 	    0),
737 	RK_COMPOSITE(RK3588_CLK_700M_SRC, "clk_700m_src",
738 	    gpll_spll_parents,
739 	    CLKSEL_CON(0, 6), __BITS(5,5), __BITS(4,0),
740 	    CLKGATE_CON(0, 0), __BIT(12),
741 	    0),
742 	RK_COMPOSITE(RK3588_CLK_800M_SRC, "clk_800m_src",
743 	    gpll_aupll_parents,
744 	    CLKSEL_CON(0, 6), __BITS(11,11), __BITS(10,6),
745 	    CLKGATE_CON(0, 0), __BIT(13),
746 	    0),
747 	RK_COMPOSITE_HALF(RK3588_CLK_1000M_SRC, "clk_1000m_src",
748 	    gpll_cpll_npll_v0pll_parents,
749 	    CLKSEL_CON(0, 7), __BITS(6,5),
750 	    __BITS(4,0),
751 	    CLKGATE_CON(0, 0), __BIT(14),
752 	    0),
753 	RK_COMPOSITE(RK3588_CLK_1200M_SRC, "clk_1200m_src",
754 	    gpll_cpll_parents,
755 	    CLKSEL_CON(0, 7), __BITS(12,12), __BITS(11,7),
756 	    CLKGATE_CON(0, 0), __BIT(15),
757 	    0),
758 	RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M300_ROOT, "aclk_top_m300_root",
759 	    mux_300m_200m_100m_24m_parents,
760 	    CLKSEL_CON(0, 9), __BITS(1,0),
761 	    CLKGATE_CON(0, 1), __BIT(10),
762 	    0),
763 	RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M500_ROOT, "aclk_top_m500_root",
764 	    mux_500m_300m_100m_24m_parents,
765 	    CLKSEL_CON(0, 9), __BITS(3,2),
766 	    CLKGATE_CON(0, 1), __BIT(11),
767 	    0),
768 	RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M400_ROOT, "aclk_top_m400_root",
769 	    mux_400m_200m_100m_24m_parents,
770 	    CLKSEL_CON(0, 9), __BITS(5,4),
771 	    CLKGATE_CON(0, 1), __BIT(12),
772 	    0),
773 	RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_S200_ROOT, "aclk_top_s200_root",
774 	    mux_200m_100m_50m_24m_parents,
775 	    CLKSEL_CON(0, 9), __BITS(7,6),
776 	    CLKGATE_CON(0, 1), __BIT(13),
777 	    0),
778 	RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_S400_ROOT, "aclk_top_s400_root",
779 	    mux_400m_200m_100m_24m_parents,
780 	    CLKSEL_CON(0, 9), __BITS(9,8),
781 	    CLKGATE_CON(0, 1), __BIT(14),
782 	    0),
783 	RK_COMPOSITE(RK3588_ACLK_TOP_ROOT, "aclk_top_root",
784 	    gpll_cpll_aupll_parents,
785 	    CLKSEL_CON(0, 8), __BITS(6,5), __BITS(4,0),
786 	    CLKGATE_CON(0, 1), __BIT(0),
787 	    0),
788 	RK_COMPOSITE_NODIV(RK3588_PCLK_TOP_ROOT, "pclk_top_root",
789 	    mux_100m_50m_24m_parents,
790 	    CLKSEL_CON(0, 8), __BITS(8,7),
791 	    CLKGATE_CON(0, 1), __BIT(1),
792 	    0),
793 	RK_COMPOSITE(RK3588_ACLK_LOW_TOP_ROOT, "aclk_low_top_root",
794 	    gpll_cpll_parents,
795 	    CLKSEL_CON(0, 8), __BITS(14,14), __BITS(13,9),
796 	    CLKGATE_CON(0, 1), __BIT(2),
797 	    0),
798 	RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0",
799 	    mux_24m_spll_gpll_cpll_parents,
800 	    CLKSEL_CON(0, 18), __BITS(9,8), __BITS(7,0),
801 	    CLKGATE_CON(0, 5), __BIT(9),
802 	    0),
803 	RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1",
804 	    mux_24m_spll_gpll_cpll_parents,
805 	    CLKSEL_CON(0, 19), __BITS(9,8), __BITS(7,0),
806 	    CLKGATE_CON(0, 5), __BIT(10),
807 	    0),
808 	RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2",
809 	    mux_24m_spll_gpll_cpll_parents,
810 	    CLKSEL_CON(0, 20), __BITS(9,8), __BITS(7,0),
811 	    CLKGATE_CON(0, 5), __BIT(11),
812 	    0),
813 	RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3",
814 	    mux_24m_spll_gpll_cpll_parents,
815 	    CLKSEL_CON(0, 21), __BITS(9,8), __BITS(7,0),
816 	    CLKGATE_CON(0, 5), __BIT(12),
817 	    0),
818 	RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4",
819 	    mux_24m_spll_gpll_cpll_parents,
820 	    CLKSEL_CON(0, 22), __BITS(9,8), __BITS(7,0),
821 	    CLKGATE_CON(0, 5), __BIT(13),
822 	    0),
823 	RK_COMPOSITE(RK3588_MCLK_GMAC0_OUT, "mclk_gmac0_out",
824 	    gpll_cpll_parents,
825 	    CLKSEL_CON(0, 15), __BITS(7,7), __BITS(6,0),
826 	    CLKGATE_CON(0, 5), __BIT(3),
827 	    0),
828 	RK_COMPOSITE(RK3588_REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out",
829 	    gpll_cpll_parents,
830 	    CLKSEL_CON(0, 15), __BITS(15,15), __BITS(14,8),
831 	    CLKGATE_CON(0, 5), __BIT(4),
832 	    0),
833 	RK_COMPOSITE(RK3588_REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out",
834 	    gpll_cpll_parents,
835 	    CLKSEL_CON(0, 16), __BITS(7,7), __BITS(6,0),
836 	    CLKGATE_CON(0, 5), __BIT(5),
837 	    0),
838 	RK_COMPOSITE(RK3588_CLK_CIFOUT_OUT, "clk_cifout_out",
839 	    gpll_cpll_24m_spll_parents,
840 	    CLKSEL_CON(0, 17), __BITS(9,8), __BITS(7,0),
841 	    CLKGATE_CON(0, 5), __BIT(6),
842 	    0),
843 	RK_GATE(RK3588_PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root",
844 	    CLKGATE_CON(0, 3), 14),
845 	RK_GATE(RK3588_PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root",
846 	    CLKGATE_CON(0, 4), 3),
847 	RK_GATE(RK3588_PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root",
848 	    CLKGATE_CON(0, 1), 6),
849 	RK_GATE(RK3588_PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root",
850 	    CLKGATE_CON(0, 1), 8),
851 	RK_GATE(RK3588_PCLK_CRU, "pclk_cru", "pclk_top_root",
852 	    CLKGATE_CON(0, 5), 0),
853 	RK_COMPOSITE(0, "sclk_dsu",
854 	    b0pll_b1pll_lpll_gpll_parents,
855 	    CLKSEL_CON(DSU, 0), __BITS(13,12), __BITS(4,0),
856 	    CLKGATE_CON(DSU, 0), __BIT(4),
857 	    0),
858 	RK_COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu",
859 	    CLKSEL_CON(DSU, 3), __BITS(4,0),
860 	    CLKGATE_CON(DSU, 1), __BIT(0),
861 	    0),
862 	RK_COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu",
863 	    CLKSEL_CON(DSU, 3), __BITS(9,5),
864 	    CLKGATE_CON(DSU, 1), __BIT(1),
865 	    0),
866 	RK_COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu",
867 	    CLKSEL_CON(DSU, 1), __BITS(15,11),
868 	    CLKGATE_CON(DSU, 0), __BIT(12),
869 	    0),
870 	RK_COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu",
871 	    CLKSEL_CON(DSU, 1), __BITS(5,1),
872 	    CLKGATE_CON(DSU, 0), __BIT(8),
873 	    0),
874 	RK_COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu",
875 	    CLKSEL_CON(DSU, 1), __BITS(10,6),
876 	    CLKGATE_CON(DSU, 0), __BIT(9),
877 	    0),
878 	RK_COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu",
879 	    CLKSEL_CON(DSU, 2), __BITS(4,0),
880 	    CLKGATE_CON(DSU, 0), __BIT(13),
881 	    0),
882 	RK_COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu",
883 	    CLKSEL_CON(DSU, 2), __BITS(9,5),
884 	    CLKGATE_CON(DSU, 0), __BIT(14),
885 	    0),
886 	RK_COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu",
887 	    CLKSEL_CON(DSU, 2), __BITS(14,10),
888 	    CLKGATE_CON(DSU, 0), __BIT(15),
889 	    0),
890 	RK_COMPOSITE_NODIV(RK3588_PCLK_DSU_S_ROOT, "pclk_dsu_s_root",
891 	    mux_100m_50m_24m_parents,
892 	    CLKSEL_CON(DSU, 4), __BITS(12,11),
893 	    CLKGATE_CON(DSU, 2), __BIT(2),
894 	    0),
895 	RK_COMPOSITE(RK3588_PCLK_DSU_ROOT, "pclk_dsu_root",
896 	    b0pll_b1pll_lpll_gpll_parents,
897 	    CLKSEL_CON(DSU, 4), __BITS(6,5), __BITS(4,0),
898 	    CLKGATE_CON(DSU, 1), __BIT(3),
899 	    0),
900 	RK_COMPOSITE_NODIV(RK3588_PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root",
901 	    mux_100m_50m_24m_parents,
902 	    CLKSEL_CON(DSU, 4), __BITS(8,7),
903 	    CLKGATE_CON(DSU, 1), __BIT(4),
904 	    0),
905 	RK_GATE(RK3588_PCLK_LITCORE_PVTM, "pclk_litcore_pvtm",
906 	    "pclk_dsu_ns_root",
907 	    CLKGATE_CON(DSU, 2), 6),
908 	RK_GATE(RK3588_PCLK_DBG, "pclk_dbg", "pclk_dsu_root",
909 	    CLKGATE_CON(DSU, 1), 7),
910 	RK_GATE(RK3588_PCLK_DSU, "pclk_dsu", "pclk_dsu_root",
911 	    CLKGATE_CON(DSU, 1), 6),
912 	RK_GATE(RK3588_PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root",
913 	    CLKGATE_CON(DSU, 1), 8),
914 	RK_GATE(RK3588_PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root",
915 	    CLKGATE_CON(DSU, 1), 9),
916 	RK_GATE(RK3588_CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m",
917 	    CLKGATE_CON(DSU, 2), 0),
918 	RK_GATE(RK3588_CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm",
919 	    "armclk_l",
920 	    CLKGATE_CON(DSU, 2), 1),
921 	RK_COMPOSITE_NODIV(RK3588_HCLK_AUDIO_ROOT, "hclk_audio_root",
922 	    mux_200m_100m_50m_24m_parents,
923 	    CLKSEL_CON(0, 24), __BITS(1,0),
924 	    CLKGATE_CON(0, 7), __BIT(0),
925 	    0),
926 	RK_COMPOSITE_NODIV(RK3588_PCLK_AUDIO_ROOT, "pclk_audio_root",
927 	    mux_100m_50m_24m_parents,
928 	    CLKSEL_CON(0, 24), __BITS(3,2),
929 	    CLKGATE_CON(0, 7), __BIT(1),
930 	    0),
931 	RK_GATE(RK3588_HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root",
932 	    CLKGATE_CON(0, 7), 12),
933 	RK_GATE(RK3588_HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root",
934 	    CLKGATE_CON(0, 7), 13),
935 	RK_COMPOSITE(RK3588_CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src",
936 	    gpll_aupll_parents,
937 	    CLKSEL_CON(0, 28), __BITS(9,9), __BITS(8,4),
938 	    CLKGATE_CON(0, 7), __BIT(14),
939 	    0),
940 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac",
941 	    "clk_i2s2_2ch_src",
942 	    CLKGATE_CON(0, 7),
943 	    RK_COMPOSITE_SET_RATE_PARENT),
944 	RK_MUX(RK3588_CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_parents,
945 	    CLKSEL_CON(0, 30), __BITS(1,0)),
946 	RK_GATE(RK3588_MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch",
947 	    CLKGATE_CON(0, 8), 0),
948 	RK_MUX(RK3588_I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout",
949 	    i2s2_2ch_mclkout_parents,
950 	    CLKSEL_CON(0, 30), __BITS(2,2)),
951 	RK_COMPOSITE(RK3588_CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src",
952 	    gpll_aupll_parents,
953 	    CLKSEL_CON(0, 30), __BITS(8,8), __BITS(7,3),
954 	    CLKGATE_CON(0, 8), __BIT(1),
955 	    0),
956 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac",
957 	    "clk_i2s3_2ch_src",
958 	    CLKGATE_CON(0, 8),
959 	    RK_COMPOSITE_SET_RATE_PARENT),
960 	RK_MUX(RK3588_CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_parents,
961 	    CLKSEL_CON(0, 32), __BITS(1,0)),
962 	RK_GATE(RK3588_MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch",
963 	    CLKGATE_CON(0, 8), 3),
964 	RK_GATE(RK3588_CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch",
965 	    CLKGATE_CON(0, 8), 4),
966 	RK_MUX(RK3588_I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout",
967 	    i2s3_2ch_mclkout_parents,
968 	    CLKSEL_CON(0, 32), __BITS(2,2)),
969 	RK_GATE(RK3588_PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root",
970 	    CLKGATE_CON(0, 7), 11),
971 	RK_GATE(RK3588_HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root",
972 	    CLKGATE_CON(0, 7), 4),
973 	RK_COMPOSITE(RK3588_CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src",
974 	    gpll_aupll_parents,
975 	    CLKSEL_CON(0, 24), __BITS(9,9), __BITS(8,4),
976 	    CLKGATE_CON(0, 7), __BIT(5),
977 	    0),
978 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac",
979 	   "clk_i2s0_8ch_tx_src",
980 	    CLKGATE_CON(0, 7),
981 	    RK_COMPOSITE_SET_RATE_PARENT),
982 	RK_MUX(RK3588_CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx",
983 	    clk_i2s0_8ch_tx_parents,
984 	    CLKSEL_CON(0, 26), __BITS(1,0)),
985 	RK_GATE(RK3588_MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx",
986 	    CLKGATE_CON(0, 7), 7),
987 	RK_COMPOSITE(RK3588_CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src",
988 	    gpll_aupll_parents,
989 	    CLKSEL_CON(0, 26), __BITS(7,7), __BITS(6,2),
990 	    CLKGATE_CON(0, 7), __BIT(8),
991 	    0),
992 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac",
993 	    "clk_i2s0_8ch_rx_src",
994 	    CLKGATE_CON(0, 7),
995 	    RK_COMPOSITE_SET_RATE_PARENT),
996 	RK_MUX(RK3588_CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx",
997 	    clk_i2s0_8ch_rx_parents,
998 	    CLKSEL_CON(0, 28), __BITS(1,0)),
999 	RK_GATE(RK3588_MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx",
1000 	    CLKGATE_CON(0, 7), 10),
1001 	RK_MUX(RK3588_I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout",
1002 	    i2s0_8ch_mclkout_parents,
1003 	    CLKSEL_CON(0, 28), __BITS(3,2)),
1004 	RK_GATE(RK3588_HCLK_PDM1, "hclk_pdm1", "hclk_audio_root",
1005 	    CLKGATE_CON(0, 9), 6),
1006 	RK_COMPOSITE(RK3588_MCLK_PDM1, "mclk_pdm1",
1007 	    gpll_cpll_aupll_parents,
1008 	    CLKSEL_CON(0, 36), __BITS(8,7), __BITS(6,2),
1009 	    CLKGATE_CON(0, 9), __BIT(7),
1010 	    0),
1011 	RK_GATE(RK3588_HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root",
1012 	    CLKGATE_CON(0, 8), 14),
1013 	RK_COMPOSITE(RK3588_CLK_SPDIF0_SRC, "clk_spdif0_src",
1014 	    gpll_aupll_parents,
1015 	    CLKSEL_CON(0, 32), __BITS(8,8), __BITS(7,3),
1016 	    CLKGATE_CON(0, 8), __BIT(15),
1017 	    0),
1018 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF0_FRAC, "clk_spdif0_frac",
1019 	    "clk_spdif0_src",
1020 	    CLKGATE_CON(0, 9),
1021 	    RK_COMPOSITE_SET_RATE_PARENT),
1022 	RK_MUX(RK3588_CLK_SPDIF0, "clk_spdif0", clk_spdif0_parents,
1023 	    CLKSEL_CON(0, 34), __BITS(1,0)),
1024 	RK_GATE(RK3588_MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0",
1025 	    CLKGATE_CON(0, 9), 1),
1026 	RK_GATE(RK3588_HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root",
1027 	    CLKGATE_CON(0, 9), 2),
1028 	RK_COMPOSITE(RK3588_CLK_SPDIF1_SRC, "clk_spdif1_src",
1029 	    gpll_aupll_parents,
1030 	    CLKSEL_CON(0, 34), __BITS(7,7), __BITS(6,2),
1031 	    CLKGATE_CON(0, 9), __BIT(3),
1032 	    0),
1033 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF1_FRAC, "clk_spdif1_frac",
1034 	    "clk_spdif1_src",
1035 	    CLKGATE_CON(0, 9),
1036 	    RK_COMPOSITE_SET_RATE_PARENT),
1037 	RK_MUX(RK3588_CLK_SPDIF1, "clk_spdif1", clk_spdif1_parents,
1038 	    CLKSEL_CON(0, 36), __BITS(1,0)),
1039 	RK_GATE(RK3588_MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1",
1040 	    CLKGATE_CON(0, 9), 5),
1041 	RK_COMPOSITE(RK3588_ACLK_AV1_ROOT, "aclk_av1_root",
1042 	    gpll_cpll_aupll_parents,
1043 	    CLKSEL_CON(0, 163), __BITS(6,5), __BITS(4,0),
1044 	    CLKGATE_CON(0, 68), __BIT(0),
1045 	    0),
1046 	RK_COMPOSITE_NODIV(RK3588_PCLK_AV1_ROOT, "pclk_av1_root",
1047 	    mux_200m_100m_50m_24m_parents,
1048 	    CLKSEL_CON(0, 163), __BITS(8,7),
1049 	    CLKGATE_CON(0, 68), __BIT(3),
1050 	    0),
1051 	RK_COMPOSITE(RK3588_ACLK_BUS_ROOT, "aclk_bus_root",
1052 	    gpll_cpll_parents,
1053 	    CLKSEL_CON(0, 38), __BITS(5,5), __BITS(4,0),
1054 	    CLKGATE_CON(0, 10), __BIT(0),
1055 	    0),
1056 	RK_GATE(RK3588_PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root",
1057 	    CLKGATE_CON(0, 16), 11),
1058 	RK_GATE(RK3588_PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root",
1059 	    CLKGATE_CON(0, 16), 12),
1060 	RK_GATE(RK3588_PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root",
1061 	    CLKGATE_CON(0, 16), 13),
1062 	RK_GATE(RK3588_PCLK_PMU2, "pclk_pmu2", "pclk_top_root",
1063 	    CLKGATE_CON(0, 19), 3),
1064 	RK_GATE(RK3588_PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux",
1065 	    "pclk_top_root",
1066 	    CLKGATE_CON(0, 19), 4),
1067 	RK_GATE(RK3588_PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux",
1068 	    "pclk_top_root",
1069 	    CLKGATE_CON(0, 19), 5),
1070 	RK_GATE(RK3588_PCLK_PWM1, "pclk_pwm1", "pclk_top_root",
1071 	    CLKGATE_CON(0, 15), 3),
1072 	RK_COMPOSITE_NODIV(RK3588_CLK_PWM1, "clk_pwm1",
1073 	    mux_100m_50m_24m_parents,
1074 	    CLKSEL_CON(0, 59), __BITS(13,12),
1075 	    CLKGATE_CON(0, 15), __BIT(4),
1076 	    0),
1077 	RK_GATE(RK3588_CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m",
1078 	    CLKGATE_CON(0, 15), 5),
1079 	RK_GATE(RK3588_PCLK_PWM2, "pclk_pwm2", "pclk_top_root",
1080 	    CLKGATE_CON(0, 15), 6),
1081 	RK_COMPOSITE_NODIV(RK3588_CLK_PWM2, "clk_pwm2",
1082 	    mux_100m_50m_24m_parents,
1083 	    CLKSEL_CON(0, 59), __BITS(15,14),
1084 	    CLKGATE_CON(0, 15), __BIT(7),
1085 	    0),
1086 	RK_GATE(RK3588_CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m",
1087 	    CLKGATE_CON(0, 15), 8),
1088 	RK_GATE(RK3588_PCLK_PWM3, "pclk_pwm3", "pclk_top_root",
1089 	    CLKGATE_CON(0, 15), 9),
1090 	RK_COMPOSITE_NODIV(RK3588_CLK_PWM3, "clk_pwm3",
1091 	    mux_100m_50m_24m_parents,
1092 	    CLKSEL_CON(0, 60), __BITS(1,0),
1093 	    CLKGATE_CON(0, 15), __BIT(10),
1094 	    0),
1095 	RK_GATE(RK3588_CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m",
1096 	    CLKGATE_CON(0, 15), 11),
1097 	RK_GATE(RK3588_PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root",
1098 	    CLKGATE_CON(0, 15), 12),
1099 	RK_GATE(RK3588_PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root",
1100 	    CLKGATE_CON(0, 15), 13),
1101 	RK_COMPOSITE_NODIV(RK3588_CLK_BUS_TIMER_ROOT, "clk_bus_timer_root",
1102 	    mux_24m_100m_parents,
1103 	    CLKSEL_CON(0, 60), __BITS(2,2),
1104 	    CLKGATE_CON(0, 15), __BIT(14),
1105 	    0),
1106 	RK_GATE(RK3588_CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root",
1107 	    CLKGATE_CON(0, 15), 15),
1108 	RK_GATE(RK3588_CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root",
1109 	    CLKGATE_CON(0, 16), 0),
1110 	RK_GATE(RK3588_CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root",
1111 	    CLKGATE_CON(0, 16), 1),
1112 	RK_GATE(RK3588_CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root",
1113 	    CLKGATE_CON(0, 16), 2),
1114 	RK_GATE(RK3588_CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root",
1115 	    CLKGATE_CON(0, 16), 3),
1116 	RK_GATE(RK3588_CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root",
1117 	    CLKGATE_CON(0, 16), 4),
1118 	RK_GATE(RK3588_CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root",
1119 	    CLKGATE_CON(0, 16), 5),
1120 	RK_GATE(RK3588_CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root",
1121 	    CLKGATE_CON(0, 16), 6),
1122 	RK_GATE(RK3588_CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root",
1123 	    CLKGATE_CON(0, 16), 7),
1124 	RK_GATE(RK3588_CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root",
1125 	    CLKGATE_CON(0, 16), 8),
1126 	RK_GATE(RK3588_CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root",
1127 	    CLKGATE_CON(0, 16), 9),
1128 	RK_GATE(RK3588_CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root",
1129 	    CLKGATE_CON(0, 16), 10),
1130 	RK_GATE(RK3588_PCLK_WDT0, "pclk_wdt0", "pclk_top_root",
1131 	    CLKGATE_CON(0, 15), 0),
1132 	RK_GATE(RK3588_TCLK_WDT0, "tclk_wdt0", "xin24m",
1133 	    CLKGATE_CON(0, 15), 1),
1134 	RK_GATE(RK3588_PCLK_CAN0, "pclk_can0", "pclk_top_root",
1135 	    CLKGATE_CON(0, 11), 8),
1136 	RK_COMPOSITE(RK3588_CLK_CAN0, "clk_can0",
1137 	    gpll_cpll_parents,
1138 	    CLKSEL_CON(0, 39), __BITS(5,5), __BITS(4,0),
1139 	    CLKGATE_CON(0, 11), __BIT(9),
1140 	    0),
1141 	RK_GATE(RK3588_PCLK_CAN1, "pclk_can1", "pclk_top_root",
1142 	    CLKGATE_CON(0, 11), 10),
1143 	RK_COMPOSITE(RK3588_CLK_CAN1, "clk_can1",
1144 	    gpll_cpll_parents,
1145 	    CLKSEL_CON(0, 39), __BITS(11,11), __BITS(10,6),
1146 	    CLKGATE_CON(0, 11), __BIT(11),
1147 	    0),
1148 	RK_GATE(RK3588_PCLK_CAN2, "pclk_can2", "pclk_top_root",
1149 	    CLKGATE_CON(0, 11), 12),
1150 	RK_COMPOSITE(RK3588_CLK_CAN2, "clk_can2",
1151 	    gpll_cpll_parents,
1152 	    CLKSEL_CON(0, 40), __BITS(5,5), __BITS(4,0),
1153 	    CLKGATE_CON(0, 11), __BIT(13),
1154 	    0),
1155 	RK_GATE(RK3588_ACLK_DECOM, "aclk_decom", "aclk_bus_root",
1156 	    CLKGATE_CON(0, 17), 6),
1157 	RK_GATE(RK3588_PCLK_DECOM, "pclk_decom", "pclk_top_root",
1158 	    CLKGATE_CON(0, 17), 7),
1159 	RK_COMPOSITE(RK3588_DCLK_DECOM, "dclk_decom",
1160 	    gpll_spll_parents,
1161 	    CLKSEL_CON(0, 62), __BITS(5,5), __BITS(4,0),
1162 	    CLKGATE_CON(0, 17), __BIT(8),
1163 	    0),
1164 	RK_GATE(RK3588_ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root",
1165 	    CLKGATE_CON(0, 10), 5),
1166 	RK_GATE(RK3588_ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root",
1167 	    CLKGATE_CON(0, 10), 6),
1168 	RK_GATE(RK3588_ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root",
1169 	    CLKGATE_CON(0, 10), 7),
1170 	RK_GATE(RK3588_ACLK_GIC, "aclk_gic", "aclk_bus_root",
1171 	    CLKGATE_CON(0, 10), 3),
1172 	RK_GATE(RK3588_PCLK_GPIO1, "pclk_gpio1", "pclk_top_root",
1173 	    CLKGATE_CON(0, 16), 14),
1174 	RK_COMPOSITE(RK3588_DBCLK_GPIO1, "dbclk_gpio1",
1175 	    mux_24m_32k_parents,
1176 	    CLKSEL_CON(0, 60), __BITS(8,8), __BITS(7,3),
1177 	    CLKGATE_CON(0, 16), __BIT(15),
1178 	    0),
1179 	RK_GATE(RK3588_PCLK_GPIO2, "pclk_gpio2", "pclk_top_root",
1180 	    CLKGATE_CON(0, 17), 0),
1181 	RK_COMPOSITE(RK3588_DBCLK_GPIO2, "dbclk_gpio2",
1182 	    mux_24m_32k_parents,
1183 	    CLKSEL_CON(0, 60), __BITS(14,14), __BITS(13,9),
1184 	    CLKGATE_CON(0, 17), __BIT(1),
1185 	    0),
1186 	RK_GATE(RK3588_PCLK_GPIO3, "pclk_gpio3", "pclk_top_root",
1187 	    CLKGATE_CON(0, 17), 2),
1188 	RK_COMPOSITE(RK3588_DBCLK_GPIO3, "dbclk_gpio3",
1189 	    mux_24m_32k_parents,
1190 	    CLKSEL_CON(0, 61), __BITS(5,5), __BITS(4,0),
1191 	    CLKGATE_CON(0, 17), __BIT(3),
1192 	    0),
1193 	RK_GATE(RK3588_PCLK_GPIO4, "pclk_gpio4", "pclk_top_root",
1194 	    CLKGATE_CON(0, 17), 4),
1195 	RK_COMPOSITE(RK3588_DBCLK_GPIO4, "dbclk_gpio4",
1196 	    mux_24m_32k_parents,
1197 	    CLKSEL_CON(0, 61), __BITS(11,11), __BITS(10,6),
1198 	    CLKGATE_CON(0, 17), __BIT(5),
1199 	    0),
1200 	RK_GATE(RK3588_PCLK_I2C1, "pclk_i2c1", "pclk_top_root",
1201 	    CLKGATE_CON(0, 10), 8),
1202 	RK_GATE(RK3588_PCLK_I2C2, "pclk_i2c2", "pclk_top_root",
1203 	    CLKGATE_CON(0, 10), 9),
1204 	RK_GATE(RK3588_PCLK_I2C3, "pclk_i2c3", "pclk_top_root",
1205 	    CLKGATE_CON(0, 10), 10),
1206 	RK_GATE(RK3588_PCLK_I2C4, "pclk_i2c4", "pclk_top_root",
1207 	    CLKGATE_CON(0, 10), 11),
1208 	RK_GATE(RK3588_PCLK_I2C5, "pclk_i2c5", "pclk_top_root",
1209 	    CLKGATE_CON(0, 10), 12),
1210 	RK_GATE(RK3588_PCLK_I2C6, "pclk_i2c6", "pclk_top_root",
1211 	    CLKGATE_CON(0, 10), 13),
1212 	RK_GATE(RK3588_PCLK_I2C7, "pclk_i2c7", "pclk_top_root",
1213 	    CLKGATE_CON(0, 10), 14),
1214 	RK_GATE(RK3588_PCLK_I2C8, "pclk_i2c8", "pclk_top_root",
1215 	    CLKGATE_CON(0, 10), 15),
1216 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C1, "clk_i2c1",
1217 	    mux_200m_100m_parents,
1218 	    CLKSEL_CON(0, 38), __BITS(6,6),
1219 	    CLKGATE_CON(0, 11), __BIT(0),
1220 	    0),
1221 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C2, "clk_i2c2",
1222 	    mux_200m_100m_parents,
1223 	    CLKSEL_CON(0, 38), __BITS(7,7),
1224 	    CLKGATE_CON(0, 11), __BIT(1),
1225 	    0),
1226 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C3, "clk_i2c3",
1227 	    mux_200m_100m_parents,
1228 	    CLKSEL_CON(0, 38), __BITS(8,8),
1229 	    CLKGATE_CON(0, 11), __BIT(2),
1230 	    0),
1231 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C4, "clk_i2c4",
1232 	    mux_200m_100m_parents,
1233 	    CLKSEL_CON(0, 38), __BITS(9,9),
1234 	    CLKGATE_CON(0, 11), __BIT(3),
1235 	    0),
1236 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C5, "clk_i2c5",
1237 	    mux_200m_100m_parents,
1238 	    CLKSEL_CON(0, 38), __BITS(10,10),
1239 	    CLKGATE_CON(0, 11), __BIT(4),
1240 	    0),
1241 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C6, "clk_i2c6",
1242 	    mux_200m_100m_parents,
1243 	    CLKSEL_CON(0, 38), __BITS(11,11),
1244 	    CLKGATE_CON(0, 11), __BIT(5),
1245 	    0),
1246 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C7, "clk_i2c7",
1247 	    mux_200m_100m_parents,
1248 	    CLKSEL_CON(0, 38), __BITS(12,12),
1249 	    CLKGATE_CON(0, 11), __BIT(6),
1250 	    0),
1251 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C8, "clk_i2c8",
1252 	    mux_200m_100m_parents,
1253 	    CLKSEL_CON(0, 38), __BITS(13,13),
1254 	    CLKGATE_CON(0, 11), __BIT(7),
1255 	    0),
1256 	RK_GATE(RK3588_PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root",
1257 	    CLKGATE_CON(0, 18), 9),
1258 	RK_GATE(RK3588_CLK_OTPC_NS, "clk_otpc_ns", "xin24m",
1259 	    CLKGATE_CON(0, 18), 10),
1260 	RK_GATE(RK3588_CLK_OTPC_ARB, "clk_otpc_arb", "xin24m",
1261 	    CLKGATE_CON(0, 18), 11),
1262 	RK_GATE(RK3588_CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m",
1263 	    CLKGATE_CON(0, 18), 13),
1264 	RK_GATE(RK3588_CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m",
1265 	    CLKGATE_CON(0, 18), 12),
1266 	RK_GATE(RK3588_PCLK_SARADC, "pclk_saradc", "pclk_top_root",
1267 	    CLKGATE_CON(0, 11), 14),
1268 	RK_COMPOSITE(RK3588_CLK_SARADC, "clk_saradc",
1269 	    gpll_24m_parents,
1270 	    CLKSEL_CON(0, 40), __BITS(14,14), __BITS(13,6),
1271 	    CLKGATE_CON(0, 11), __BIT(15),
1272 	    0),
1273 	RK_GATE(RK3588_PCLK_SPI0, "pclk_spi0", "pclk_top_root",
1274 	    CLKGATE_CON(0, 14), 6),
1275 	RK_GATE(RK3588_PCLK_SPI1, "pclk_spi1", "pclk_top_root",
1276 	    CLKGATE_CON(0, 14), 7),
1277 	RK_GATE(RK3588_PCLK_SPI2, "pclk_spi2", "pclk_top_root",
1278 	    CLKGATE_CON(0, 14), 8),
1279 	RK_GATE(RK3588_PCLK_SPI3, "pclk_spi3", "pclk_top_root",
1280 	    CLKGATE_CON(0, 14), 9),
1281 	RK_GATE(RK3588_PCLK_SPI4, "pclk_spi4", "pclk_top_root",
1282 	    CLKGATE_CON(0, 14), 10),
1283 	RK_COMPOSITE_NODIV(RK3588_CLK_SPI0, "clk_spi0",
1284 	    mux_200m_150m_24m_parents,
1285 	    CLKSEL_CON(0, 59), __BITS(3,2),
1286 	    CLKGATE_CON(0, 14), __BIT(11),
1287 	    0),
1288 	RK_COMPOSITE_NODIV(RK3588_CLK_SPI1, "clk_spi1",
1289 	    mux_200m_150m_24m_parents,
1290 	    CLKSEL_CON(0, 59), __BITS(5,4),
1291 	    CLKGATE_CON(0, 14), __BIT(12),
1292 	    0),
1293 	RK_COMPOSITE_NODIV(RK3588_CLK_SPI2, "clk_spi2",
1294 	    mux_200m_150m_24m_parents,
1295 	    CLKSEL_CON(0, 59), __BITS(7,6),
1296 	    CLKGATE_CON(0, 14), __BIT(13),
1297 	    0),
1298 	RK_COMPOSITE_NODIV(RK3588_CLK_SPI3, "clk_spi3",
1299 	    mux_200m_150m_24m_parents,
1300 	    CLKSEL_CON(0, 59), __BITS(9,8),
1301 	    CLKGATE_CON(0, 14), __BIT(14),
1302 	    0),
1303 	RK_COMPOSITE_NODIV(RK3588_CLK_SPI4, "clk_spi4",
1304 	    mux_200m_150m_24m_parents,
1305 	    CLKSEL_CON(0, 59), __BITS(11,10),
1306 	    CLKGATE_CON(0, 14), __BIT(15),
1307 	    0),
1308 	RK_GATE(RK3588_ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root",
1309 	    CLKGATE_CON(0, 18), 6),
1310 	RK_GATE(RK3588_PCLK_TSADC, "pclk_tsadc", "pclk_top_root",
1311 	    CLKGATE_CON(0, 12), 0),
1312 	RK_COMPOSITE(RK3588_CLK_TSADC, "clk_tsadc",
1313 	    gpll_24m_parents,
1314 	    CLKSEL_CON(0, 41), __BITS(8,8), __BITS(7,0),
1315 	    CLKGATE_CON(0, 12), __BIT(1),
1316 	    0),
1317 	RK_GATE(RK3588_PCLK_UART1, "pclk_uart1", "pclk_top_root",
1318 	    CLKGATE_CON(0, 12), 2),
1319 	RK_GATE(RK3588_PCLK_UART2, "pclk_uart2", "pclk_top_root",
1320 	    CLKGATE_CON(0, 12), 3),
1321 	RK_GATE(RK3588_PCLK_UART3, "pclk_uart3", "pclk_top_root",
1322 	    CLKGATE_CON(0, 12), 4),
1323 	RK_GATE(RK3588_PCLK_UART4, "pclk_uart4", "pclk_top_root",
1324 	    CLKGATE_CON(0, 12), 5),
1325 	RK_GATE(RK3588_PCLK_UART5, "pclk_uart5", "pclk_top_root",
1326 	    CLKGATE_CON(0, 12), 6),
1327 	RK_GATE(RK3588_PCLK_UART6, "pclk_uart6", "pclk_top_root",
1328 	    CLKGATE_CON(0, 12), 7),
1329 	RK_GATE(RK3588_PCLK_UART7, "pclk_uart7", "pclk_top_root",
1330 	    CLKGATE_CON(0, 12), 8),
1331 	RK_GATE(RK3588_PCLK_UART8, "pclk_uart8", "pclk_top_root",
1332 	    CLKGATE_CON(0, 12), 9),
1333 	RK_GATE(RK3588_PCLK_UART9, "pclk_uart9", "pclk_top_root",
1334 	    CLKGATE_CON(0, 12), 10),
1335 	RK_COMPOSITE(RK3588_CLK_UART1_SRC, "clk_uart1_src",
1336 	    gpll_cpll_parents,
1337 	    CLKSEL_CON(0, 41), __BITS(14,14), __BITS(13,9),
1338 	    CLKGATE_CON(0, 12), __BIT(11),
1339 	    0),
1340 	RK_COMPOSITE_FRAC(RK3588_CLK_UART1_FRAC, "clk_uart1_frac",
1341 	    "clk_uart1_src",
1342 	    CLKGATE_CON(0, 12),
1343 	    RK_COMPOSITE_SET_RATE_PARENT),
1344 	RK_MUX(RK3588_CLK_UART1, "clk_uart1", clk_uart1_parents,
1345 	    CLKSEL_CON(0, 43), __BITS(1,0)),
1346 	RK_GATE(RK3588_SCLK_UART1, "sclk_uart1", "clk_uart1",
1347 	    CLKGATE_CON(0, 12), 13),
1348 	RK_COMPOSITE(RK3588_CLK_UART2_SRC, "clk_uart2_src",
1349 	    gpll_cpll_parents,
1350 	    CLKSEL_CON(0, 43), __BITS(7,7), __BITS(6,2),
1351 	    CLKGATE_CON(0, 12), __BIT(14),
1352 	    0),
1353 	RK_COMPOSITE_FRAC(RK3588_CLK_UART2_FRAC, "clk_uart2_frac",
1354 	    "clk_uart2_src",
1355 	    CLKGATE_CON(0, 12),
1356 	    RK_COMPOSITE_SET_RATE_PARENT),
1357 	RK_MUX(RK3588_CLK_UART2, "clk_uart2", clk_uart2_parents,
1358 	    CLKSEL_CON(0, 45), __BITS(1,0)),
1359 	RK_GATE(RK3588_SCLK_UART2, "sclk_uart2", "clk_uart2",
1360 	    CLKGATE_CON(0, 13), 0),
1361 	RK_COMPOSITE(RK3588_CLK_UART3_SRC, "clk_uart3_src",
1362 	    gpll_cpll_parents,
1363 	    CLKSEL_CON(0, 45), __BITS(7,7), __BITS(6,2),
1364 	    CLKGATE_CON(0, 13), __BIT(1),
1365 	    0),
1366 	RK_COMPOSITE_FRAC(RK3588_CLK_UART3_FRAC, "clk_uart3_frac",
1367 	    "clk_uart3_src",
1368 	    CLKGATE_CON(0, 13),
1369 	    RK_COMPOSITE_SET_RATE_PARENT),
1370 	RK_MUX(RK3588_CLK_UART3, "clk_uart3", clk_uart3_parents,
1371 	    CLKSEL_CON(0, 47), __BITS(1,0)),
1372 	RK_GATE(RK3588_SCLK_UART3, "sclk_uart3", "clk_uart3",
1373 	    CLKGATE_CON(0, 13), 3),
1374 	RK_COMPOSITE(RK3588_CLK_UART4_SRC, "clk_uart4_src",
1375 	    gpll_cpll_parents,
1376 	    CLKSEL_CON(0, 47), __BITS(7,7), __BITS(6,2),
1377 	    CLKGATE_CON(0, 13), __BIT(4),
1378 	    0),
1379 	RK_COMPOSITE_FRAC(RK3588_CLK_UART4_FRAC, "clk_uart4_frac",
1380 	    "clk_uart4_src",
1381 	    CLKGATE_CON(0, 13),
1382 	    RK_COMPOSITE_SET_RATE_PARENT),
1383 	RK_MUX(RK3588_CLK_UART4, "clk_uart4", clk_uart4_parents,
1384 	    CLKSEL_CON(0, 49), __BITS(1,0)),
1385 	RK_GATE(RK3588_SCLK_UART4, "sclk_uart4", "clk_uart4",
1386 	    CLKGATE_CON(0, 13), 6),
1387 	RK_COMPOSITE(RK3588_CLK_UART5_SRC, "clk_uart5_src",
1388 	    gpll_cpll_parents,
1389 	    CLKSEL_CON(0, 49), __BITS(7,7), __BITS(6,2),
1390 	    CLKGATE_CON(0, 13), __BIT(7),
1391 	    0),
1392 	RK_COMPOSITE_FRAC(RK3588_CLK_UART5_FRAC, "clk_uart5_frac",
1393 	    "clk_uart5_src",
1394 	    CLKGATE_CON(0, 13),
1395 	    RK_COMPOSITE_SET_RATE_PARENT),
1396 	RK_MUX(RK3588_CLK_UART5, "clk_uart5", clk_uart5_parents,
1397 	    CLKSEL_CON(0, 51), __BITS(1,0)),
1398 	RK_GATE(RK3588_SCLK_UART5, "sclk_uart5", "clk_uart5",
1399 	    CLKGATE_CON(0, 13), 9),
1400 	RK_COMPOSITE(RK3588_CLK_UART6_SRC, "clk_uart6_src",
1401 	    gpll_cpll_parents,
1402 	    CLKSEL_CON(0, 51), __BITS(7,7), __BITS(6,2),
1403 	    CLKGATE_CON(0, 13), __BIT(10),
1404 	    0),
1405 	RK_COMPOSITE_FRAC(RK3588_CLK_UART6_FRAC, "clk_uart6_frac",
1406 	    "clk_uart6_src",
1407 	    CLKGATE_CON(0, 13),
1408 	    RK_COMPOSITE_SET_RATE_PARENT),
1409 	RK_MUX(RK3588_CLK_UART6, "clk_uart6", clk_uart6_parents,
1410 	    CLKSEL_CON(0, 53), __BITS(1,0)),
1411 	RK_GATE(RK3588_SCLK_UART6, "sclk_uart6", "clk_uart6",
1412 	    CLKGATE_CON(0, 13), 12),
1413 	RK_COMPOSITE(RK3588_CLK_UART7_SRC, "clk_uart7_src",
1414 	    gpll_cpll_parents,
1415 	    CLKSEL_CON(0, 53), __BITS(7,7), __BITS(6,2),
1416 	    CLKGATE_CON(0, 13), __BIT(13),
1417 	    0),
1418 	RK_COMPOSITE_FRAC(RK3588_CLK_UART7_FRAC, "clk_uart7_frac",
1419 	    "clk_uart7_src",
1420 	    CLKGATE_CON(0, 13),
1421 	    RK_COMPOSITE_SET_RATE_PARENT),
1422 	RK_MUX(RK3588_CLK_UART7, "clk_uart7", clk_uart7_parents,
1423 	    CLKSEL_CON(0, 55), __BITS(1,0)),
1424 	RK_GATE(RK3588_SCLK_UART7, "sclk_uart7", "clk_uart7",
1425 	    CLKGATE_CON(0, 13), 15),
1426 	RK_COMPOSITE(RK3588_CLK_UART8_SRC, "clk_uart8_src",
1427 	    gpll_cpll_parents,
1428 	    CLKSEL_CON(0, 55), __BITS(7,7), __BITS(6,2),
1429 	    CLKGATE_CON(0, 14), __BIT(0),
1430 	    0),
1431 	RK_COMPOSITE_FRAC(RK3588_CLK_UART8_FRAC, "clk_uart8_frac",
1432 	    "clk_uart8_src",
1433 	    CLKGATE_CON(0, 14),
1434 	    RK_COMPOSITE_SET_RATE_PARENT),
1435 	RK_MUX(RK3588_CLK_UART8, "clk_uart8", clk_uart8_parents,
1436 	    CLKSEL_CON(0, 57), __BITS(1,0)),
1437 	RK_GATE(RK3588_SCLK_UART8, "sclk_uart8", "clk_uart8",
1438 	    CLKGATE_CON(0, 14), 2),
1439 	RK_COMPOSITE(RK3588_CLK_UART9_SRC, "clk_uart9_src",
1440 	    gpll_cpll_parents,
1441 	    CLKSEL_CON(0, 57), __BITS(7,7), __BITS(6,2),
1442 	    CLKGATE_CON(0, 14), __BIT(3),
1443 	    0),
1444 	RK_COMPOSITE_FRAC(RK3588_CLK_UART9_FRAC, "clk_uart9_frac",
1445 	    "clk_uart9_src",
1446 	    CLKGATE_CON(0, 14),
1447 	    RK_COMPOSITE_SET_RATE_PARENT),
1448 	RK_MUX(RK3588_CLK_UART9, "clk_uart9", clk_uart9_parents,
1449 	    CLKSEL_CON(0, 59), __BITS(1,0)),
1450 	RK_GATE(RK3588_SCLK_UART9, "sclk_uart9", "clk_uart9",
1451 	    CLKGATE_CON(0, 14), 5),
1452 	RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_ROOT, "aclk_center_root",
1453 	    mux_700m_400m_200m_24m_parents,
1454 	    CLKSEL_CON(0, 165), __BITS(1,0),
1455 	    CLKGATE_CON(0, 69), __BIT(0),
1456 	    0),
1457 	RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_LOW_ROOT, "aclk_center_low_root",
1458 	    mux_500m_250m_100m_24m_parents,
1459 	    CLKSEL_CON(0, 165), __BITS(3,2),
1460 	    CLKGATE_CON(0, 69), __BIT(1),
1461 	    0),
1462 	RK_COMPOSITE_NODIV(RK3588_HCLK_CENTER_ROOT, "hclk_center_root",
1463 	    mux_400m_200m_100m_24m_parents,
1464 	    CLKSEL_CON(0, 165), __BITS(5,4),
1465 	    CLKGATE_CON(0, 69), __BIT(2),
1466 	    0),
1467 	RK_COMPOSITE_NODIV(RK3588_PCLK_CENTER_ROOT, "pclk_center_root",
1468 	    mux_200m_100m_50m_24m_parents,
1469 	    CLKSEL_CON(0, 165), __BITS(7,6),
1470 	    CLKGATE_CON(0, 69), __BIT(3),
1471 	    0),
1472 	RK_GATE(RK3588_ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root",
1473 	    CLKGATE_CON(0, 69), 5),
1474 	RK_GATE(RK3588_ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem",
1475 	    "aclk_center_low_root",
1476 	    CLKGATE_CON(0, 69), 6),
1477 	RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_S200_ROOT,
1478 	    "aclk_center_s200_root",
1479 	    mux_200m_100m_50m_24m_parents,
1480 	    CLKSEL_CON(0, 165), __BITS(9,8),
1481 	    CLKGATE_CON(0, 69), __BIT(8),
1482 	    0),
1483 	RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_S400_ROOT,
1484 	    "aclk_center_s400_root", mux_400m_200m_100m_24m_parents,
1485 	    CLKSEL_CON(0, 165), __BITS(11,10),
1486 	    CLKGATE_CON(0, 69), __BIT(9),
1487 	    0),
1488 	RK_GATE(RK3588_FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core",
1489 	    "hclk_center_root",
1490 	    CLKGATE_CON(0, 69), 14),
1491 	RK_COMPOSITE_NODIV(RK3588_CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root",
1492 	    mux_24m_100m_parents,
1493 	    CLKSEL_CON(0, 165), __BITS(12,12),
1494 	    CLKGATE_CON(0, 69), __BIT(15),
1495 	    0),
1496 	RK_GATE(RK3588_CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root",
1497 	    CLKGATE_CON(0, 70), 0),
1498 	RK_GATE(RK3588_CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root",
1499 	    CLKGATE_CON(0, 70), 1),
1500 	RK_GATE(RK3588_TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m",
1501 	    CLKGATE_CON(0, 70), 2),
1502 	RK_COMPOSITE(RK3588_CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc",
1503 	    mux_24m_32k_parents,
1504 	    CLKSEL_CON(0, 166), __BITS(5,5), __BITS(4,0),
1505 	    CLKGATE_CON(0, 70), __BIT(4),
1506 	    0),
1507 	RK_GATE(RK3588_PCLK_WDT, "pclk_wdt", "pclk_center_root",
1508 	    CLKGATE_CON(0, 70), 7),
1509 	RK_GATE(RK3588_PCLK_TIMER, "pclk_timer", "pclk_center_root",
1510 	    CLKGATE_CON(0, 70), 8),
1511 	RK_GATE(RK3588_PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root",
1512 	    CLKGATE_CON(0, 70), 9),
1513 	RK_GATE(RK3588_PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root",
1514 	    CLKGATE_CON(0, 70), 10),
1515 	RK_COMPOSITE(RK3588_CLK_GPU_SRC, "clk_gpu_src",
1516 	    gpll_cpll_aupll_npll_spll_parents,
1517 	    CLKSEL_CON(0, 158), __BITS(7,5), __BITS(4,0),
1518 	    CLKGATE_CON(0, 66), __BIT(1),
1519 	    0),
1520 	RK_GATE(RK3588_CLK_GPU, "clk_gpu", "clk_gpu_src",
1521 	    CLKGATE_CON(0, 66), 4),
1522 	RK_GATE(RK3588_CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src",
1523 	    CLKGATE_CON(0, 66), 6),
1524 	RK_COMPOSITE_NOMUX(RK3588_CLK_GPU_STACKS, "clk_gpu_stacks",
1525 	    "clk_gpu_src",
1526 	    CLKSEL_CON(0, 159), __BITS(4,0),
1527 	    CLKGATE_CON(0, 66), __BIT(7),
1528 	    0),
1529 	RK_GATE(RK3588_CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m",
1530 	    CLKGATE_CON(0, 67), 0),
1531 	RK_GATE(RK3588_CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src",
1532 	    CLKGATE_CON(0, 67), 1),
1533 	RK_COMPOSITE(RK3588_ACLK_ISP1_ROOT, "aclk_isp1_root",
1534 	    gpll_cpll_aupll_spll_parents,
1535 	    CLKSEL_CON(0, 67), __BITS(6,5), __BITS(4,0),
1536 	    CLKGATE_CON(0, 26), __BIT(0),
1537 	    0),
1538 	RK_COMPOSITE_NODIV(RK3588_HCLK_ISP1_ROOT, "hclk_isp1_root",
1539 	    mux_200m_100m_50m_24m_parents,
1540 	    CLKSEL_CON(0, 67), __BITS(8,7),
1541 	    CLKGATE_CON(0, 26), __BIT(1),
1542 	    0),
1543 	RK_COMPOSITE(RK3588_CLK_ISP1_CORE, "clk_isp1_core",
1544 	    gpll_cpll_aupll_spll_parents,
1545 	    CLKSEL_CON(0, 67), __BITS(15,14), __BITS(13,9),
1546 	    CLKGATE_CON(0, 26), __BIT(2),
1547 	    0),
1548 	RK_GATE(RK3588_CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin",
1549 	    "clk_isp1_core",
1550 	    CLKGATE_CON(0, 26), 3),
1551 	RK_GATE(RK3588_CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap",
1552 	    "clk_isp1_core",
1553 	    CLKGATE_CON(0, 26), 4),
1554 	RK_COMPOSITE_NODIV(RK3588_HCLK_NPU_ROOT, "hclk_npu_root",
1555 	    mux_200m_100m_50m_24m_parents,
1556 	    CLKSEL_CON(0, 73), __BITS(1,0),
1557 	    CLKGATE_CON(0, 29), __BIT(0),
1558 	    0),
1559 	RK_COMPOSITE(RK3588_CLK_NPU_DSU0, "clk_npu_dsu0",
1560 	    gpll_cpll_aupll_npll_spll_parents,
1561 	    CLKSEL_CON(0, 73), __BITS(9,7), __BITS(6,2),
1562 	    CLKGATE_CON(0, 29), __BIT(1),
1563 	    0),
1564 	RK_COMPOSITE_NODIV(RK3588_PCLK_NPU_ROOT, "pclk_npu_root",
1565 	    mux_100m_50m_24m_parents,
1566 	    CLKSEL_CON(0, 74), __BITS(2,1),
1567 	    CLKGATE_CON(0, 29), __BIT(4),
1568 	    0),
1569 	RK_GATE(RK3588_ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0",
1570 	    CLKGATE_CON(0, 27), 0),
1571 	RK_GATE(RK3588_HCLK_NPU1, "hclk_npu1", "hclk_npu_root",
1572 	    CLKGATE_CON(0, 27), 2),
1573 	RK_GATE(RK3588_ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0",
1574 	    CLKGATE_CON(0, 28), 0),
1575 	RK_GATE(RK3588_HCLK_NPU2, "hclk_npu2", "hclk_npu_root",
1576 	    CLKGATE_CON(0, 28), 2),
1577 	RK_COMPOSITE_NODIV(RK3588_HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root",
1578 	    mux_400m_200m_100m_24m_parents,
1579 	    CLKSEL_CON(0, 74), __BITS(6,5),
1580 	    CLKGATE_CON(0, 30), __BIT(1),
1581 	    0),
1582 	RK_GATE(RK3588_FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core",
1583 	    "hclk_npu_cm0_root",
1584 	    CLKGATE_CON(0, 30), 3),
1585 	RK_COMPOSITE(RK3588_CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc",
1586 	    mux_24m_32k_parents,
1587 	    CLKSEL_CON(0, 74), __BITS(12,12), __BITS(11,7),
1588 	    CLKGATE_CON(0, 30), __BIT(5),
1589 	    0),
1590 	RK_GATE(RK3588_PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root",
1591 	    CLKGATE_CON(0, 29), 12),
1592 	RK_GATE(RK3588_PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root",
1593 	    CLKGATE_CON(0, 29), 13),
1594 	RK_GATE(RK3588_CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m",
1595 	    CLKGATE_CON(0, 29), 14),
1596 	RK_GATE(RK3588_CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0",
1597 	    CLKGATE_CON(0, 29), 15),
1598 	RK_GATE(RK3588_ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0",
1599 	    CLKGATE_CON(0, 30), 6),
1600 	RK_GATE(RK3588_HCLK_NPU0, "hclk_npu0", "hclk_npu_root",
1601 	    CLKGATE_CON(0, 30), 8),
1602 	RK_GATE(RK3588_PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root",
1603 	    CLKGATE_CON(0, 29), 6),
1604 	RK_COMPOSITE_NODIV(RK3588_CLK_NPUTIMER_ROOT, "clk_nputimer_root",
1605 	    mux_24m_100m_parents,
1606 	    CLKSEL_CON(0, 74), __BITS(3,3),
1607 	    CLKGATE_CON(0, 29), __BIT(7),
1608 	    0),
1609 	RK_GATE(RK3588_CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root",
1610 	    CLKGATE_CON(0, 29), 8),
1611 	RK_GATE(RK3588_CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root",
1612 	    CLKGATE_CON(0, 29), 9),
1613 	RK_GATE(RK3588_PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root",
1614 	    CLKGATE_CON(0, 29), 10),
1615 	RK_GATE(RK3588_TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m",
1616 	    CLKGATE_CON(0, 29), 11),
1617 	RK_COMPOSITE_NODIV(RK3588_HCLK_NVM_ROOT, "hclk_nvm_root",
1618 	    mux_200m_100m_50m_24m_parents,
1619 	    CLKSEL_CON(0, 77), __BITS(1,0),
1620 	    CLKGATE_CON(0, 31), __BIT(0),
1621 	    0),
1622 	RK_COMPOSITE(RK3588_ACLK_NVM_ROOT, "aclk_nvm_root",
1623 	    gpll_cpll_parents,
1624 	    CLKSEL_CON(0, 77), __BITS(7,7), __BITS(6,2),
1625 	    CLKGATE_CON(0, 31), __BIT(1),
1626 	    0),
1627 	RK_GATE(RK3588_ACLK_EMMC, "aclk_emmc", "aclk_nvm_root",
1628 	    CLKGATE_CON(0, 31), 5),
1629 	RK_COMPOSITE(RK3588_CCLK_EMMC, "cclk_emmc",
1630 	    gpll_cpll_24m_parents,
1631 	    CLKSEL_CON(0, 77), __BITS(15,14), __BITS(13,8),
1632 	    CLKGATE_CON(0, 31), __BIT(6),
1633 	    0),
1634 	RK_COMPOSITE(RK3588_BCLK_EMMC, "bclk_emmc",
1635 	    gpll_cpll_parents,
1636 	    CLKSEL_CON(0, 78), __BITS(5,5), __BITS(4,0),
1637 	    CLKGATE_CON(0, 31), __BIT(7),
1638 	    0),
1639 	RK_GATE(RK3588_TMCLK_EMMC, "tmclk_emmc", "xin24m",
1640 	    CLKGATE_CON(0, 31), 8),
1641 	RK_COMPOSITE(RK3588_SCLK_SFC, "sclk_sfc",
1642 	    gpll_cpll_24m_parents,
1643 	    CLKSEL_CON(0, 78), __BITS(13,12), __BITS(11,6),
1644 	    CLKGATE_CON(0, 31), __BIT(9),
1645 	    0),
1646 	RK_COMPOSITE(RK3588_CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref",
1647 	    clk_gmac0_ptp_ref_parents,
1648 	    CLKSEL_CON(0, 81), __BITS(6,6), __BITS(5,0),
1649 	    CLKGATE_CON(0, 34), __BIT(10),
1650 	    0),
1651 	RK_COMPOSITE(RK3588_CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref",
1652 	    clk_gmac1_ptp_ref_parents,
1653 	    CLKSEL_CON(0, 81), __BITS(13,13), __BITS(12,7),
1654 	    CLKGATE_CON(0, 34), __BIT(11),
1655 	    0),
1656 	RK_COMPOSITE(RK3588_CLK_GMAC_125M, "clk_gmac_125m",
1657 	    gpll_cpll_parents,
1658 	    CLKSEL_CON(0, 83), __BITS(15,15), __BITS(14,8),
1659 	    CLKGATE_CON(0, 35), __BIT(5),
1660 	    0),
1661 	RK_COMPOSITE(RK3588_CLK_GMAC_50M, "clk_gmac_50m",
1662 	    gpll_cpll_parents,
1663 	    CLKSEL_CON(0, 84), __BITS(7,7), __BITS(6,0),
1664 	    CLKGATE_CON(0, 35), __BIT(6),
1665 	    0),
1666 	RK_COMPOSITE(RK3588_ACLK_PCIE_ROOT, "aclk_pcie_root",
1667 	    gpll_cpll_parents,
1668 	    CLKSEL_CON(0, 80), __BITS(7,7), __BITS(6,2),
1669 	    CLKGATE_CON(0, 32), __BIT(6),
1670 	    0),
1671 	RK_COMPOSITE(RK3588_ACLK_PHP_ROOT, "aclk_php_root",
1672 	    gpll_cpll_parents,
1673 	    CLKSEL_CON(0, 80), __BITS(13,13), __BITS(12,8),
1674 	    CLKGATE_CON(0, 32), __BIT(7),
1675 	    0),
1676 	RK_COMPOSITE_NODIV(RK3588_PCLK_PHP_ROOT, "pclk_php_root",
1677 	    mux_150m_50m_24m_parents,
1678 	    CLKSEL_CON(0, 80), __BITS(1,0),
1679 	    CLKGATE_CON(0, 32), __BIT(0),
1680 	    0),
1681 	RK_GATE(RK3588_ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root",
1682 	    CLKGATE_CON(0, 34), 6),
1683 	RK_GATE(RK3588_ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root",
1684 	    CLKGATE_CON(0, 32), 8),
1685 	RK_GATE(RK3588_ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge",
1686 	    CLKGATE_CON(0, 34), 7),
1687 	RK_GATE(RK3588_ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root",
1688 	    CLKGATE_CON(0, 34), 8),
1689 	RK_GATE(RK3588_ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root",
1690 	    CLKGATE_CON(0, 32), 13),
1691 	RK_GATE(RK3588_ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root",
1692 	    CLKGATE_CON(0, 32), 14),
1693 	RK_GATE(RK3588_ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root",
1694 	    CLKGATE_CON(0, 32), 15),
1695 	RK_GATE(RK3588_ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root",
1696 	    CLKGATE_CON(0, 33), 0),
1697 	RK_GATE(RK3588_ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root",
1698 	    CLKGATE_CON(0, 33), 1),
1699 	RK_GATE(RK3588_ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie",
1700 	    CLKGATE_CON(0, 33), 2),
1701 	RK_GATE(RK3588_ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie",
1702 	    CLKGATE_CON(0, 33), 3),
1703 	RK_GATE(RK3588_ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr",
1704 	    "aclk_mmu_pcie",
1705 	    CLKGATE_CON(0, 33), 4),
1706 	RK_GATE(RK3588_ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr",
1707 	    "aclk_mmu_pcie",
1708 	    CLKGATE_CON(0, 33), 5),
1709 	RK_GATE(RK3588_ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr",
1710 	    "aclk_mmu_pcie",
1711 	    CLKGATE_CON(0, 33), 6),
1712 	RK_GATE(RK3588_ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root",
1713 	    CLKGATE_CON(0, 33), 7),
1714 	RK_GATE(RK3588_ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root",
1715 	    CLKGATE_CON(0, 33), 8),
1716 	RK_GATE(RK3588_ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root",
1717 	    CLKGATE_CON(0, 33), 9),
1718 	RK_GATE(RK3588_ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root",
1719 	    CLKGATE_CON(0, 33), 10),
1720 	RK_GATE(RK3588_ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root",
1721 	    CLKGATE_CON(0, 33), 11),
1722 	RK_GATE(RK3588_PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root",
1723 	    CLKGATE_CON(0, 33), 12),
1724 	RK_GATE(RK3588_PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root",
1725 	    CLKGATE_CON(0, 33), 13),
1726 	RK_GATE(RK3588_PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root",
1727 	    CLKGATE_CON(0, 33), 14),
1728 	RK_GATE(RK3588_PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root",
1729 	    CLKGATE_CON(0, 33), 15),
1730 	RK_GATE(RK3588_PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root",
1731 	    CLKGATE_CON(0, 34), 0),
1732 	RK_GATE(RK3588_CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m",
1733 	    CLKGATE_CON(0, 34), 1),
1734 	RK_GATE(RK3588_CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m",
1735 	    CLKGATE_CON(0, 34), 2),
1736 	RK_GATE(RK3588_CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m",
1737 	    CLKGATE_CON(0, 34), 3),
1738 	RK_GATE(RK3588_CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m",
1739 	    CLKGATE_CON(0, 34), 4),
1740 	RK_GATE(RK3588_CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m",
1741 	    CLKGATE_CON(0, 34), 5),
1742 	RK_GATE(RK3588_CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m",
1743 	    CLKGATE_CON(0, 37), 0),
1744 	RK_GATE(RK3588_CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m",
1745 	    CLKGATE_CON(0, 37), 1),
1746 	RK_GATE(RK3588_CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m",
1747 	    CLKGATE_CON(0, 37), 2),
1748 	RK_GATE(RK3588_PCLK_GMAC0, "pclk_gmac0", "pclk_php_root",
1749 	    CLKGATE_CON(0, 32), 3),
1750 	RK_GATE(RK3588_PCLK_GMAC1, "pclk_gmac1", "pclk_php_root",
1751 	    CLKGATE_CON(0, 32), 4),
1752 	RK_GATE(RK3588_ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php",
1753 	    CLKGATE_CON(0, 32), 10),
1754 	RK_GATE(RK3588_ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php",
1755 	    CLKGATE_CON(0, 32), 11),
1756 	RK_GATE(RK3588_CLK_PMALIVE0, "clk_pmalive0", "xin24m",
1757 	    CLKGATE_CON(0, 37), 4),
1758 	RK_GATE(RK3588_CLK_PMALIVE1, "clk_pmalive1", "xin24m",
1759 	    CLKGATE_CON(0, 37), 5),
1760 	RK_GATE(RK3588_CLK_PMALIVE2, "clk_pmalive2", "xin24m",
1761 	    CLKGATE_CON(0, 37), 6),
1762 	RK_GATE(RK3588_ACLK_SATA0, "aclk_sata0", "aclk_mmu_php",
1763 	    CLKGATE_CON(0, 37), 7),
1764 	RK_GATE(RK3588_ACLK_SATA1, "aclk_sata1", "aclk_mmu_php",
1765 	    CLKGATE_CON(0, 37), 8),
1766 	RK_GATE(RK3588_ACLK_SATA2, "aclk_sata2", "aclk_mmu_php",
1767 	    CLKGATE_CON(0, 37), 9),
1768 	RK_COMPOSITE(RK3588_CLK_RXOOB0, "clk_rxoob0",
1769 	    gpll_cpll_parents,
1770 	    CLKSEL_CON(0, 82), __BITS(7,7), __BITS(6,0),
1771 	    CLKGATE_CON(0, 37), __BIT(10),
1772 	    0),
1773 	RK_COMPOSITE(RK3588_CLK_RXOOB1, "clk_rxoob1",
1774 	    gpll_cpll_parents,
1775 	    CLKSEL_CON(0, 82), __BITS(15,15), __BITS(14,8),
1776 	    CLKGATE_CON(0, 37), __BIT(11),
1777 	    0),
1778 	RK_COMPOSITE(RK3588_CLK_RXOOB2, "clk_rxoob2",
1779 	    gpll_cpll_parents,
1780 	    CLKSEL_CON(0, 83), __BITS(7,7), __BITS(6,0),
1781 	    CLKGATE_CON(0, 37), __BIT(12),
1782 	    0),
1783 	RK_GATE(RK3588_ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php",
1784 	    CLKGATE_CON(0, 35), 7),
1785 	RK_GATE(RK3588_SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m",
1786 	    CLKGATE_CON(0, 35), 8),
1787 	RK_GATE(RK3588_REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m",
1788 	    CLKGATE_CON(0, 35), 9),
1789 	RK_COMPOSITE(RK3588_CLK_UTMI_OTG2, "clk_utmi_otg2",
1790 	    mux_150m_50m_24m_parents,
1791 	    CLKSEL_CON(0, 84), __BITS(13,12), __BITS(11,8),
1792 	    CLKGATE_CON(0, 35), __BIT(10),
1793 	    0),
1794 	RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0",
1795 	    "pclk_top_root",
1796 	    CLKGATE_CON(PHP, 0), 5),
1797 	RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1",
1798 	    "pclk_top_root",
1799 	    CLKGATE_CON(PHP, 0), 6),
1800 	RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2",
1801 	    "pclk_top_root",
1802 	    CLKGATE_CON(PHP, 0), 7),
1803 	RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy",
1804 	    "pclk_top_root",
1805 	    CLKGATE_CON(PHP, 0), 8),
1806 	RK_COMPOSITE(RK3588_CLK_RGA3_1_CORE, "clk_rga3_1_core",
1807 	    gpll_cpll_aupll_spll_parents,
1808 	    CLKSEL_CON(0, 174), __BITS(15,14), __BITS(13,9),
1809 	    CLKGATE_CON(0, 76), __BIT(6),
1810 	    0),
1811 	RK_COMPOSITE(RK3588_ACLK_RGA3_ROOT, "aclk_rga3_root",
1812 	    gpll_cpll_aupll_parents,
1813 	    CLKSEL_CON(0, 174), __BITS(6,5), __BITS(4,0),
1814 	    CLKGATE_CON(0, 76), __BIT(0),
1815 	    0),
1816 	RK_COMPOSITE_NODIV(RK3588_HCLK_RGA3_ROOT, "hclk_rga3_root",
1817 	    mux_200m_100m_50m_24m_parents,
1818 	    CLKSEL_CON(0, 174), __BITS(8,7),
1819 	    CLKGATE_CON(0, 76), __BIT(1),
1820 	    0),
1821 	RK_GATE(RK3588_HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root",
1822 	    CLKGATE_CON(0, 76), 4),
1823 	RK_GATE(RK3588_ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root",
1824 	    CLKGATE_CON(0, 76), 5),
1825 	RK_COMPOSITE_NODIV(0, "hclk_rkvdec0_root",
1826 	    mux_200m_100m_50m_24m_parents,
1827 	    CLKSEL_CON(0, 89), __BITS(1,0),
1828 	    CLKGATE_CON(0, 40), __BIT(0),
1829 	    0),
1830 	RK_COMPOSITE(0, "aclk_rkvdec0_root",
1831 	    gpll_cpll_aupll_spll_parents,
1832 	    CLKSEL_CON(0, 89), __BITS(8,7), __BITS(6,2),
1833 	    CLKGATE_CON(0, 40), __BIT(1),
1834 	    0),
1835 	RK_COMPOSITE(RK3588_ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu",
1836 	    gpll_cpll_aupll_spll_parents,
1837 	    CLKSEL_CON(0, 89), __BITS(15,14), __BITS(13,9),
1838 	    CLKGATE_CON(0, 40), __BIT(2),
1839 	    0),
1840 	RK_COMPOSITE(RK3588_CLK_RKVDEC0_CA, "clk_rkvdec0_ca",
1841 	    gpll_cpll_parents,
1842 	    CLKSEL_CON(0, 90), __BITS(5,5), __BITS(4,0),
1843 	    CLKGATE_CON(0, 40), __BIT(7),
1844 	    0),
1845 	RK_COMPOSITE(RK3588_CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca",
1846 	    gpll_cpll_npll_1000m_parents,
1847 	    CLKSEL_CON(0, 90), __BITS(12,11), __BITS(10,6),
1848 	    CLKGATE_CON(0, 40), __BIT(8),
1849 	    0),
1850 	RK_COMPOSITE(RK3588_CLK_RKVDEC0_CORE, "clk_rkvdec0_core",
1851 	    gpll_cpll_parents,
1852 	    CLKSEL_CON(0, 91), __BITS(5,5), __BITS(4,0),
1853 	    CLKGATE_CON(0, 40), __BIT(9),
1854 	    0),
1855 	RK_COMPOSITE_NODIV(0, "hclk_rkvdec1_root",
1856 	    mux_200m_100m_50m_24m_parents,
1857 	    CLKSEL_CON(0, 93), __BITS(1,0),
1858 	    CLKGATE_CON(0, 41), __BIT(0),
1859 	    0),
1860 	RK_COMPOSITE(0, "aclk_rkvdec1_root",
1861 	    gpll_cpll_aupll_npll_parents,
1862 	    CLKSEL_CON(0, 93), __BITS(8,7), __BITS(6,2),
1863 	    CLKGATE_CON(0, 41), __BIT(1),
1864 	    0),
1865 	RK_COMPOSITE(RK3588_CLK_RKVDEC1_CA, "clk_rkvdec1_ca",
1866 	    gpll_cpll_parents,
1867 	    CLKSEL_CON(0, 93), __BITS(14,14), __BITS(13,9),
1868 	    CLKGATE_CON(0, 41), __BIT(6),
1869 	    0),
1870 	RK_COMPOSITE(RK3588_CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca",
1871 	    gpll_cpll_npll_1000m_parents,
1872 	    CLKSEL_CON(0, 94), __BITS(6,5), __BITS(4,0),
1873 	    CLKGATE_CON(0, 41), __BIT(7),
1874 	    0),
1875 	RK_COMPOSITE(RK3588_CLK_RKVDEC1_CORE, "clk_rkvdec1_core",
1876 	    gpll_cpll_parents,
1877 	    CLKSEL_CON(0, 94), __BITS(12,12), __BITS(11,7),
1878 	    CLKGATE_CON(0, 41), __BIT(8),
1879 	    0),
1880 	RK_COMPOSITE_NODIV(0, "hclk_sdio_root",
1881 	    mux_200m_100m_50m_24m_parents,
1882 	    CLKSEL_CON(0, 172), __BITS(1,0),
1883 	    CLKGATE_CON(0, 75), __BIT(0),
1884 	    0),
1885 	RK_COMPOSITE(RK3588_CCLK_SRC_SDIO, "cclk_src_sdio",
1886 	    gpll_cpll_24m_parents,
1887 	    CLKSEL_CON(0, 172), __BITS(9,8), __BITS(7,2),
1888 	    CLKGATE_CON(0, 75), __BIT(3),
1889 	    0),
1890 	RK_COMPOSITE(RK3588_ACLK_USB_ROOT, "aclk_usb_root",
1891 	    gpll_cpll_parents,
1892 	    CLKSEL_CON(0, 96), __BITS(5,5), __BITS(4,0),
1893 	    CLKGATE_CON(0, 42), __BIT(0),
1894 	    0),
1895 	RK_COMPOSITE_NODIV(RK3588_HCLK_USB_ROOT, "hclk_usb_root",
1896 	    mux_150m_100m_50m_24m_parents,
1897 	    CLKSEL_CON(0, 96), __BITS(7,6),
1898 	    CLKGATE_CON(0, 42), __BIT(1),
1899 	    0),
1900 	RK_GATE(RK3588_SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m",
1901 	    CLKGATE_CON(0, 42), 5),
1902 	RK_GATE(RK3588_REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m",
1903 	    CLKGATE_CON(0, 42), 6),
1904 	RK_GATE(RK3588_SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m",
1905 	    CLKGATE_CON(0, 42), 8),
1906 	RK_GATE(RK3588_REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m",
1907 	    CLKGATE_CON(0, 42), 9),
1908 	RK_COMPOSITE(RK3588_ACLK_VDPU_ROOT, "aclk_vdpu_root",
1909 	    gpll_cpll_aupll_parents,
1910 	    CLKSEL_CON(0, 98), __BITS(6,5), __BITS(4,0),
1911 	    CLKGATE_CON(0, 44), __BIT(0),
1912 	    0),
1913 	RK_COMPOSITE_NODIV(RK3588_ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root",
1914 	    mux_400m_200m_100m_24m_parents,
1915 	    CLKSEL_CON(0, 98), __BITS(8,7),
1916 	    CLKGATE_CON(0, 44), __BIT(1),
1917 	    0),
1918 	RK_COMPOSITE_NODIV(RK3588_HCLK_VDPU_ROOT, "hclk_vdpu_root",
1919 	    mux_200m_100m_50m_24m_parents,
1920 	    CLKSEL_CON(0, 98), __BITS(10,9),
1921 	    CLKGATE_CON(0, 44), __BIT(2),
1922 	    0),
1923 	RK_COMPOSITE(RK3588_ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root",
1924 	    gpll_cpll_aupll_spll_parents,
1925 	    CLKSEL_CON(0, 99), __BITS(6,5), __BITS(4,0),
1926 	    CLKGATE_CON(0, 44), __BIT(3),
1927 	    0),
1928 	RK_GATE(RK3588_HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root",
1929 	    CLKGATE_CON(0, 45), 4),
1930 	RK_COMPOSITE(RK3588_CLK_IEP2P0_CORE, "clk_iep2p0_core",
1931 	    gpll_cpll_parents,
1932 	    CLKSEL_CON(0, 99), __BITS(12,12), __BITS(11,7),
1933 	    CLKGATE_CON(0, 45), __BIT(6),
1934 	    0),
1935 	RK_GATE(RK3588_HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0",
1936 	    "hclk_vdpu_root",
1937 	    CLKGATE_CON(0, 44), 11),
1938 	RK_GATE(RK3588_HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1",
1939 	    "hclk_vdpu_root",
1940 	    CLKGATE_CON(0, 44), 13),
1941 	RK_GATE(RK3588_HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2",
1942 	    "hclk_vdpu_root",
1943 	    CLKGATE_CON(0, 44), 15),
1944 	RK_GATE(RK3588_HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3",
1945 	    "hclk_vdpu_root",
1946 	    CLKGATE_CON(0, 45), 1),
1947 	RK_GATE(RK3588_HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root",
1948 	    CLKGATE_CON(0, 45), 3),
1949 	RK_GATE(RK3588_HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root",
1950 	    CLKGATE_CON(0, 45), 7),
1951 	RK_GATE(RK3588_ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root",
1952 	    CLKGATE_CON(0, 45), 8),
1953 	RK_COMPOSITE(RK3588_CLK_RGA2_CORE, "clk_rga2_core",
1954 	    gpll_cpll_npll_aupll_spll_parents,
1955 	    CLKSEL_CON(0, 100), __BITS(7,5), __BITS(4,0),
1956 	    CLKGATE_CON(0, 45), __BIT(9),
1957 	    0),
1958 	RK_GATE(RK3588_HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root",
1959 	    CLKGATE_CON(0, 45), 10),
1960 	RK_GATE(RK3588_ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root",
1961 	    CLKGATE_CON(0, 45), 11),
1962 	RK_COMPOSITE(RK3588_CLK_RGA3_0_CORE, "clk_rga3_0_core",
1963 	    gpll_cpll_npll_aupll_spll_parents,
1964 	    CLKSEL_CON(0, 100), __BITS(15,13), __BITS(12,8),
1965 	    CLKGATE_CON(0, 45), __BIT(12),
1966 	    0),
1967 	RK_GATE(RK3588_HCLK_VPU, "hclk_vpu", "hclk_vdpu_root",
1968 	    CLKGATE_CON(0, 44), 9),
1969 	RK_COMPOSITE_NODIV(RK3588_HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root",
1970 	    mux_200m_100m_50m_24m_parents,
1971 	    CLKSEL_CON(0, 104), __BITS(1,0),
1972 	    CLKGATE_CON(0, 48), __BIT(0),
1973 	    0),
1974 	RK_COMPOSITE(RK3588_ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root",
1975 	    gpll_cpll_npll_parents,
1976 	    CLKSEL_CON(0, 104), __BITS(8,7), __BITS(6,2),
1977 	    CLKGATE_CON(0, 48), __BIT(1),
1978 	    0),
1979 	RK_COMPOSITE_NODIV(RK3588_HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root",
1980 	    mux_200m_100m_50m_24m_parents,
1981 	    CLKSEL_CON(0, 102), __BITS(1,0),
1982 	    CLKGATE_CON(0, 47), __BIT(0),
1983 	    0),
1984 	RK_COMPOSITE(RK3588_ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root",
1985 	    gpll_cpll_npll_parents,
1986 	    CLKSEL_CON(0, 102), __BITS(8,7), __BITS(6,2),
1987 	    CLKGATE_CON(0, 47), __BIT(1),
1988 	    0),
1989 	RK_GATE(RK3588_HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root",
1990 	    CLKGATE_CON(0, 47), 4),
1991 	RK_GATE(RK3588_ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root",
1992 	    CLKGATE_CON(0, 47), 5),
1993 	RK_COMPOSITE(RK3588_CLK_RKVENC0_CORE, "clk_rkvenc0_core",
1994 	    gpll_cpll_aupll_npll_parents,
1995 	    CLKSEL_CON(0, 102), __BITS(15,14), __BITS(13,9),
1996 	    CLKGATE_CON(0, 47), __BIT(6),
1997 	    0),
1998 	RK_COMPOSITE(RK3588_CLK_RKVENC1_CORE, "clk_rkvenc1_core",
1999 	    gpll_cpll_aupll_npll_parents,
2000 	    CLKSEL_CON(0, 104), __BITS(15,14), __BITS(13,9),
2001 	    CLKGATE_CON(0, 48), __BIT(6),
2002 	    0),
2003 	RK_COMPOSITE(RK3588_ACLK_VI_ROOT, "aclk_vi_root",
2004 	    gpll_cpll_npll_aupll_spll_parents,
2005 	    CLKSEL_CON(0, 106), __BITS(7,5), __BITS(4,0),
2006 	    CLKGATE_CON(0, 49), __BIT(0),
2007 	    0),
2008 	RK_COMPOSITE_NODIV(RK3588_HCLK_VI_ROOT, "hclk_vi_root",
2009 	    mux_200m_100m_50m_24m_parents,
2010 	    CLKSEL_CON(0, 106), __BITS(9,8),
2011 	    CLKGATE_CON(0, 49), __BIT(1),
2012 	    0),
2013 	RK_COMPOSITE_NODIV(RK3588_PCLK_VI_ROOT, "pclk_vi_root",
2014 	    mux_100m_50m_24m_parents,
2015 	    CLKSEL_CON(0, 106), __BITS(11,10),
2016 	    CLKGATE_CON(0, 49), __BIT(2),
2017 	    0),
2018 	RK_COMPOSITE_NODIV(RK3588_ICLK_CSIHOST01, "iclk_csihost01",
2019 	    mux_400m_200m_100m_24m_parents,
2020 	    CLKSEL_CON(0, 108), __BITS(15,14),
2021 	    CLKGATE_CON(0, 51), __BIT(10),
2022 	    0),
2023 	RK_GATE(RK3588_ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01",
2024 	    CLKGATE_CON(0, 51), 11),
2025 	RK_GATE(RK3588_ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01",
2026 	    CLKGATE_CON(0, 51), 12),
2027 	RK_GATE(RK3588_PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root",
2028 	    CLKGATE_CON(0, 50), 4),
2029 	RK_GATE(RK3588_PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root",
2030 	    CLKGATE_CON(0, 50), 5),
2031 	RK_GATE(RK3588_PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root",
2032 	    CLKGATE_CON(0, 50), 6),
2033 	RK_GATE(RK3588_PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root",
2034 	    CLKGATE_CON(0, 50), 7),
2035 	RK_GATE(RK3588_PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root",
2036 	    CLKGATE_CON(0, 50), 8),
2037 	RK_GATE(RK3588_PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root",
2038 	    CLKGATE_CON(0, 50), 9),
2039 	RK_GATE(RK3588_ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root",
2040 	    CLKGATE_CON(0, 49), 14),
2041 	RK_GATE(RK3588_HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root",
2042 	    CLKGATE_CON(0, 49), 15),
2043 	RK_COMPOSITE(RK3588_CLK_FISHEYE0_CORE, "clk_fisheye0_core",
2044 	    gpll_cpll_aupll_spll_parents,
2045 	    CLKSEL_CON(0, 108), __BITS(6,5), __BITS(4,0),
2046 	    CLKGATE_CON(0, 50), __BIT(0),
2047 	    0),
2048 	RK_GATE(RK3588_ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root",
2049 	    CLKGATE_CON(0, 50), 1),
2050 	RK_GATE(RK3588_HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root",
2051 	    CLKGATE_CON(0, 50), 2),
2052 	RK_COMPOSITE(RK3588_CLK_FISHEYE1_CORE, "clk_fisheye1_core",
2053 	    gpll_cpll_aupll_spll_parents,
2054 	    CLKSEL_CON(0, 108), __BITS(13,12), __BITS(11,7),
2055 	    CLKGATE_CON(0, 50), __BIT(3),
2056 	    0),
2057 	RK_COMPOSITE(RK3588_CLK_ISP0_CORE, "clk_isp0_core",
2058 	    gpll_cpll_aupll_spll_parents,
2059 	    CLKSEL_CON(0, 107), __BITS(12,11), __BITS(10,6),
2060 	    CLKGATE_CON(0, 49), __BIT(9),
2061 	    0),
2062 	RK_GATE(RK3588_CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin",
2063 	    "clk_isp0_core",
2064 	    CLKGATE_CON(0, 49), 10),
2065 	RK_GATE(RK3588_CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap",
2066 	    "clk_isp0_core",
2067 	    CLKGATE_CON(0, 49), 11),
2068 	RK_GATE(RK3588_ACLK_ISP0, "aclk_isp0", "aclk_vi_root",
2069 	    CLKGATE_CON(0, 49), 12),
2070 	RK_GATE(RK3588_HCLK_ISP0, "hclk_isp0", "hclk_vi_root",
2071 	    CLKGATE_CON(0, 49), 13),
2072 	RK_COMPOSITE(RK3588_DCLK_VICAP, "dclk_vicap",
2073 	    gpll_cpll_parents,
2074 	    CLKSEL_CON(0, 107), __BITS(5,5), __BITS(4,0),
2075 	    CLKGATE_CON(0, 49), __BIT(6),
2076 	    0),
2077 	RK_GATE(RK3588_ACLK_VICAP, "aclk_vicap", "aclk_vi_root",
2078 	    CLKGATE_CON(0, 49), 7),
2079 	RK_GATE(RK3588_HCLK_VICAP, "hclk_vicap", "hclk_vi_root",
2080 	    CLKGATE_CON(0, 49), 8),
2081 	RK_COMPOSITE(RK3588_ACLK_VO0_ROOT, "aclk_vo0_root",
2082 	    gpll_cpll_parents,
2083 	    CLKSEL_CON(0, 116), __BITS(5,5), __BITS(4,0),
2084 	    CLKGATE_CON(0, 55), __BIT(0),
2085 	    0),
2086 	RK_COMPOSITE_NODIV(RK3588_HCLK_VO0_ROOT, "hclk_vo0_root",
2087 	    mux_200m_100m_50m_24m_parents,
2088 	    CLKSEL_CON(0, 116), __BITS(7,6),
2089 	    CLKGATE_CON(0, 55), __BIT(1),
2090 	    0),
2091 	RK_COMPOSITE_NODIV(RK3588_HCLK_VO0_S_ROOT, "hclk_vo0_s_root",
2092 	    mux_200m_100m_50m_24m_parents,
2093 	    CLKSEL_CON(0, 116), __BITS(9,8),
2094 	    CLKGATE_CON(0, 55), __BIT(2),
2095 	    0),
2096 	RK_COMPOSITE_NODIV(RK3588_PCLK_VO0_ROOT, "pclk_vo0_root",
2097 	    mux_100m_50m_24m_parents,
2098 	    CLKSEL_CON(0, 116), __BITS(11,10),
2099 	    CLKGATE_CON(0, 55), __BIT(3),
2100 	    0),
2101 	RK_COMPOSITE_NODIV(RK3588_PCLK_VO0_S_ROOT, "pclk_vo0_s_root",
2102 	    mux_100m_50m_24m_parents,
2103 	    CLKSEL_CON(0, 116), __BITS(13,12),
2104 	    CLKGATE_CON(0, 55), __BIT(4),
2105 	    0),
2106 	RK_GATE(RK3588_PCLK_DP0, "pclk_dp0", "pclk_vo0_root",
2107 	    CLKGATE_CON(0, 56), 4),
2108 	RK_GATE(RK3588_PCLK_DP1, "pclk_dp1", "pclk_vo0_root",
2109 	    CLKGATE_CON(0, 56), 5),
2110 	RK_GATE(RK3588_PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root",
2111 	    CLKGATE_CON(0, 56), 6),
2112 	RK_GATE(RK3588_PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root",
2113 	    CLKGATE_CON(0, 56), 7),
2114 	RK_GATE(RK3588_CLK_DP0, "clk_dp0", "aclk_vo0_root",
2115 	    CLKGATE_CON(0, 56), 8),
2116 	RK_GATE(RK3588_CLK_DP1, "clk_dp1", "aclk_vo0_root",
2117 	    CLKGATE_CON(0, 56), 9),
2118 	RK_GATE(RK3588_HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root",
2119 	    CLKGATE_CON(0, 55), 11),
2120 	RK_GATE(RK3588_PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root",
2121 	    CLKGATE_CON(0, 55), 14),
2122 	RK_GATE(RK3588_ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root",
2123 	    CLKGATE_CON(0, 56), 0),
2124 	RK_GATE(RK3588_PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root",
2125 	    CLKGATE_CON(0, 56), 1),
2126 	RK_GATE(RK3588_PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root",
2127 	    CLKGATE_CON(0, 55), 10),
2128 	RK_COMPOSITE(RK3588_CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src",
2129 	    gpll_aupll_parents,
2130 	    CLKSEL_CON(0, 118), __BITS(5,5), __BITS(4,0),
2131 	    CLKGATE_CON(0, 56), __BIT(11),
2132 	    0),
2133 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac",
2134 	    "clk_i2s4_8ch_tx_src",
2135 	    CLKGATE_CON(0, 56),
2136 	    RK_COMPOSITE_SET_RATE_PARENT),
2137 	RK_MUX(RK3588_CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx",
2138 	    clk_i2s4_8ch_tx_parents,
2139 	    CLKSEL_CON(0, 120), __BITS(1,0)),
2140 	RK_GATE(RK3588_MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx",
2141 	    CLKGATE_CON(0, 56), 13),
2142 	RK_COMPOSITE(RK3588_CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src",
2143 	    gpll_aupll_parents,
2144 	    CLKSEL_CON(0, 120), __BITS(8,8), __BITS(7,3),
2145 	    CLKGATE_CON(0, 56), __BIT(15),
2146 	    0),
2147 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac",
2148 	    "clk_i2s8_8ch_tx_src",
2149 	    CLKGATE_CON(0, 57),
2150 	    RK_COMPOSITE_SET_RATE_PARENT),
2151 	RK_MUX(RK3588_CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx",
2152 	    clk_i2s8_8ch_tx_parents,
2153 	    CLKSEL_CON(0, 122), __BITS(1,0)),
2154 	RK_GATE(RK3588_MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx",
2155 	    CLKGATE_CON(0, 57), 1),
2156 	RK_COMPOSITE(RK3588_CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src",
2157 	    gpll_aupll_parents,
2158 	    CLKSEL_CON(0, 122), __BITS(8,8), __BITS(7,3),
2159 	    CLKGATE_CON(0, 57), __BIT(3),
2160 	    0),
2161 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac",
2162 	    "clk_spdif2_dp0_src",
2163 	    CLKGATE_CON(0, 57),
2164 	    RK_COMPOSITE_SET_RATE_PARENT),
2165 	RK_MUX(RK3588_CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_parents,
2166 	    CLKSEL_CON(0, 124), __BITS(1,0)),
2167 	RK_GATE(RK3588_MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0",
2168 	    CLKGATE_CON(0, 57), 5),
2169 	RK_GATE(RK3588_MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0",
2170 	    CLKGATE_CON(0, 57), 6),
2171 	RK_COMPOSITE(RK3588_CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src",
2172 	    gpll_aupll_parents,
2173 	    CLKSEL_CON(0, 124), __BITS(7,7), __BITS(6,2),
2174 	    CLKGATE_CON(0, 57), __BIT(8),
2175 	    0),
2176 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac",
2177 	    "clk_spdif5_dp1_src",
2178 	    CLKGATE_CON(0, 57),
2179 	    RK_COMPOSITE_SET_RATE_PARENT),
2180 	RK_MUX(RK3588_CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_parents,
2181 	    CLKSEL_CON(0, 126), __BITS(1,0)),
2182 	RK_GATE(RK3588_MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1",
2183 	    CLKGATE_CON(0, 57), 10),
2184 	RK_GATE(RK3588_MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1",
2185 	    CLKGATE_CON(0, 57), 11),
2186 	RK_COMPOSITE_NOMUX(RK3588_CLK_AUX16M_0, "clk_aux16m_0", "gpll",
2187 	    CLKSEL_CON(0, 117), __BITS(7,0),
2188 	    CLKGATE_CON(0, 56), __BIT(2),
2189 	    0),
2190 	RK_COMPOSITE_NOMUX(RK3588_CLK_AUX16M_1, "clk_aux16m_1", "gpll",
2191 	    CLKSEL_CON(0, 117), __BITS(15,8),
2192 	    CLKGATE_CON(0, 56), __BIT(3),
2193 	    0),
2194 	RK_COMPOSITE_HALF(RK3588_CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc",
2195 	    gpll_cpll_parents,
2196 	    CLKSEL_CON(0, 157), __BITS(7,7),
2197 	    __BITS(6,2),
2198 	    CLKGATE_CON(0, 65), __BIT(9),
2199 	    0),
2200 	RK_COMPOSITE(RK3588_ACLK_HDCP1_ROOT, "aclk_hdcp1_root",
2201 	    aclk_hdcp1_root_parents,
2202 	    CLKSEL_CON(0, 128), __BITS(6,5), __BITS(4,0),
2203 	    CLKGATE_CON(0, 59), __BIT(0),
2204 	    0),
2205 	RK_COMPOSITE(RK3588_ACLK_HDMIRX_ROOT, "aclk_hdmirx_root",
2206 	    gpll_cpll_parents,
2207 	    CLKSEL_CON(0, 128), __BITS(12,12), __BITS(11,7),
2208 	    CLKGATE_CON(0, 59), __BIT(1),
2209 	    0),
2210 	RK_COMPOSITE_NODIV(RK3588_HCLK_VO1_ROOT, "hclk_vo1_root",
2211 	    mux_200m_100m_50m_24m_parents,
2212 	    CLKSEL_CON(0, 128), __BITS(14,13),
2213 	    CLKGATE_CON(0, 59), __BIT(2),
2214 	    0),
2215 	RK_COMPOSITE_NODIV(RK3588_HCLK_VO1_S_ROOT, "hclk_vo1_s_root",
2216 	    mux_200m_100m_50m_24m_parents,
2217 	    CLKSEL_CON(0, 129), __BITS(1,0),
2218 	    CLKGATE_CON(0, 59), __BIT(3),
2219 	    0),
2220 	RK_COMPOSITE_NODIV(RK3588_PCLK_VO1_ROOT, "pclk_vo1_root",
2221 	    mux_150m_100m_24m_parents,
2222 	    CLKSEL_CON(0, 129), __BITS(3,2),
2223 	    CLKGATE_CON(0, 59), __BIT(4),
2224 	    0),
2225 	RK_COMPOSITE_NODIV(RK3588_PCLK_VO1_S_ROOT, "pclk_vo1_s_root",
2226 	    mux_100m_50m_24m_parents,
2227 	    CLKSEL_CON(0, 129), __BITS(5,4),
2228 	    CLKGATE_CON(0, 59), __BIT(5),
2229 	    0),
2230 	RK_COMPOSITE(RK3588_ACLK_VOP_ROOT, "aclk_vop_root",
2231 	    gpll_cpll_dmyaupll_npll_spll_parents,
2232 	    CLKSEL_CON(0, 110), __BITS(7,5), __BITS(4,0),
2233 	    CLKGATE_CON(0, 52), __BIT(0),
2234 	    0),
2235 	RK_COMPOSITE_NODIV(RK3588_ACLK_VOP_LOW_ROOT, "aclk_vop_low_root",
2236 	    mux_400m_200m_100m_24m_parents,
2237 	    CLKSEL_CON(0, 110), __BITS(9,8),
2238 	    CLKGATE_CON(0, 52), __BIT(1),
2239 	    0),
2240 	RK_COMPOSITE_NODIV(RK3588_HCLK_VOP_ROOT, "hclk_vop_root",
2241 	    mux_200m_100m_50m_24m_parents,
2242 	    CLKSEL_CON(0, 110), __BITS(11,10),
2243 	    CLKGATE_CON(0, 52), __BIT(2),
2244 	    0),
2245 	RK_COMPOSITE_NODIV(RK3588_PCLK_VOP_ROOT, "pclk_vop_root",
2246 	    mux_100m_50m_24m_parents,
2247 	    CLKSEL_CON(0, 110), __BITS(13,12),
2248 	    CLKGATE_CON(0, 52), __BIT(3),
2249 	    0),
2250 	RK_COMPOSITE(RK3588_ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root",
2251 	    gpll_cpll_parents,
2252 	    CLKSEL_CON(0, 170), __BITS(5,5), __BITS(4,0),
2253 	    CLKGATE_CON(0, 74), __BIT(0),
2254 	    0),
2255 	RK_COMPOSITE_NODIV(RK3588_HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root",
2256 	    mux_200m_100m_50m_24m_parents,
2257 	    CLKSEL_CON(0, 170), __BITS(7,6),
2258 	    CLKGATE_CON(0, 74), __BIT(2),
2259 	    0),
2260 	RK_MUX(RK3588_ACLK_VOP_SUB_SRC, "aclk_vop_sub_src",
2261 	    aclk_vop_sub_src_parents,
2262 	    CLKSEL_CON(0, 115), __BITS(9,9)),
2263 	RK_GATE(RK3588_PCLK_EDP0, "pclk_edp0", "pclk_vo1_root",
2264 	    CLKGATE_CON(0, 62), 0),
2265 	RK_GATE(RK3588_CLK_EDP0_24M, "clk_edp0_24m", "xin24m",
2266 	    CLKGATE_CON(0, 62), 1),
2267 	RK_COMPOSITE_NODIV(RK3588_CLK_EDP0_200M, "clk_edp0_200m",
2268 	    mux_200m_100m_50m_24m_parents,
2269 	    CLKSEL_CON(0, 140), __BITS(2,1),
2270 	    CLKGATE_CON(0, 62), __BIT(2),
2271 	    0),
2272 	RK_GATE(RK3588_PCLK_EDP1, "pclk_edp1", "pclk_vo1_root",
2273 	    CLKGATE_CON(0, 62), 3),
2274 	RK_GATE(RK3588_CLK_EDP1_24M, "clk_edp1_24m", "xin24m",
2275 	    CLKGATE_CON(0, 62), 4),
2276 	RK_COMPOSITE_NODIV(RK3588_CLK_EDP1_200M, "clk_edp1_200m",
2277 	    mux_200m_100m_50m_24m_parents,
2278 	    CLKSEL_CON(0, 140), __BITS(4,3),
2279 	    CLKGATE_CON(0, 62), __BIT(5),
2280 	    0),
2281 	RK_GATE(RK3588_HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root",
2282 	    CLKGATE_CON(0, 60), 4),
2283 	RK_GATE(RK3588_PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root",
2284 	    CLKGATE_CON(0, 60), 7),
2285 	RK_GATE(RK3588_ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root",
2286 	    CLKGATE_CON(0, 61), 9),
2287 	RK_GATE(RK3588_PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root",
2288 	    CLKGATE_CON(0, 61), 10),
2289 	RK_GATE(RK3588_CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root",
2290 	    CLKGATE_CON(0, 61), 11),
2291 	RK_COMPOSITE(RK3588_CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src",
2292 	    gpll_aupll_parents,
2293 	    CLKSEL_CON(0, 138), __BITS(8,8), __BITS(7,0),
2294 	    CLKGATE_CON(0, 61), __BIT(12),
2295 	    0),
2296 	RK_COMPOSITE_FRAC(RK3588_CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac",
2297 	    "clk_hdmirx_aud_src",
2298 	    CLKGATE_CON(0, 61),
2299 	    RK_COMPOSITE_SET_RATE_PARENT),
2300 	RK_GATE(RK3588_CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux",
2301 	    CLKGATE_CON(0, 61), 14),
2302 	RK_GATE(RK3588_PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root",
2303 	    CLKGATE_CON(0, 60), 11),
2304 	RK_COMPOSITE(RK3588_CLK_HDMITX0_EARC, "clk_hdmitx0_earc",
2305 	    gpll_cpll_parents,
2306 	    CLKSEL_CON(0, 133), __BITS(6,6), __BITS(5,1),
2307 	    CLKGATE_CON(0, 60), __BIT(15),
2308 	    0),
2309 	RK_GATE(RK3588_CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root",
2310 	    CLKGATE_CON(0, 61), 0),
2311 	RK_GATE(RK3588_PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root",
2312 	    CLKGATE_CON(0, 61), 2),
2313 	RK_COMPOSITE(RK3588_CLK_HDMITX1_EARC, "clk_hdmitx1_earc",
2314 	    gpll_cpll_parents,
2315 	    CLKSEL_CON(0, 136), __BITS(6,6), __BITS(5,1),
2316 	    CLKGATE_CON(0, 61), __BIT(6),
2317 	    0),
2318 	RK_GATE(RK3588_CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root",
2319 	    CLKGATE_CON(0, 61), 7),
2320 	RK_GATE(RK3588_ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root",
2321 	    CLKGATE_CON(0, 60), 9),
2322 	RK_GATE(RK3588_PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root",
2323 	    CLKGATE_CON(0, 60), 10),
2324 	RK_GATE(0, "pclk_vo1grf", "pclk_vo1_root",
2325 	    CLKGATE_CON(0, 59), 12),
2326 	RK_GATE(RK3588_PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root",
2327 	    CLKGATE_CON(0, 59), 14),
2328 	RK_GATE(RK3588_PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root",
2329 	    CLKGATE_CON(0, 59), 15),
2330 	RK_GATE(RK3588_PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root",
2331 	    CLKGATE_CON(0, 65), 8),
2332 	RK_COMPOSITE(RK3588_CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src",
2333 	    gpll_aupll_parents,
2334 	    CLKSEL_CON(0, 155), __BITS(8,8), __BITS(7,3),
2335 	    CLKGATE_CON(0, 65), __BIT(5),
2336 	    0),
2337 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac",
2338 	    "clk_i2s10_8ch_rx_src",
2339 	    CLKGATE_CON(0, 65),
2340 	    RK_COMPOSITE_SET_RATE_PARENT),
2341 	RK_MUX(RK3588_CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx",
2342 	    clk_i2s10_8ch_rx_parents,
2343 	    CLKSEL_CON(0, 157), __BITS(1,0)),
2344 	RK_GATE(RK3588_MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx",
2345 	    "clk_i2s10_8ch_rx",
2346 	    CLKGATE_CON(0, 65), 7),
2347 	RK_COMPOSITE(RK3588_CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src",
2348 	    gpll_aupll_parents,
2349 	    CLKSEL_CON(0, 129), __BITS(11,11), __BITS(10,6),
2350 	    CLKGATE_CON(0, 60), __BIT(1),
2351 	    0),
2352 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac",
2353 	    "clk_i2s7_8ch_rx_src",
2354 	    CLKGATE_CON(0, 60),
2355 	    RK_COMPOSITE_SET_RATE_PARENT),
2356 	RK_MUX(RK3588_CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx",
2357 	    clk_i2s7_8ch_rx_parents,
2358 	    CLKSEL_CON(0, 131), __BITS(1,0)),
2359 	RK_GATE(RK3588_MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx",
2360 	    CLKGATE_CON(0, 60), 3),
2361 	RK_COMPOSITE(RK3588_CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src",
2362 	    gpll_aupll_parents,
2363 	    CLKSEL_CON(0, 153), __BITS(12,12), __BITS(11,7),
2364 	    CLKGATE_CON(0, 65), __BIT(1),
2365 	    0),
2366 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac",
2367 	    "clk_i2s9_8ch_rx_src",
2368 	    CLKGATE_CON(0, 65),
2369 	    RK_COMPOSITE_SET_RATE_PARENT),
2370 	RK_MUX(RK3588_CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx",
2371 	    clk_i2s9_8ch_rx_parents,
2372 	    CLKSEL_CON(0, 155), __BITS(1,0)),
2373 	RK_GATE(RK3588_MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx",
2374 	    CLKGATE_CON(0, 65), 3),
2375 	RK_COMPOSITE(RK3588_CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src",
2376 	    gpll_aupll_parents,
2377 	    CLKSEL_CON(0, 140), __BITS(10,10), __BITS(9,5),
2378 	    CLKGATE_CON(0, 62), __BIT(6),
2379 	    0),
2380 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac",
2381 	    "clk_i2s5_8ch_tx_src",
2382 	    CLKGATE_CON(0, 62),
2383 	    RK_COMPOSITE_SET_RATE_PARENT),
2384 	RK_MUX(RK3588_CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx",
2385 	    clk_i2s5_8ch_tx_parents,
2386 	    CLKSEL_CON(0, 142), __BITS(1,0)),
2387 	RK_GATE(RK3588_MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx",
2388 	    CLKGATE_CON(0, 62), 8),
2389 	RK_COMPOSITE(RK3588_CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src",
2390 	    gpll_aupll_parents,
2391 	    CLKSEL_CON(0, 144), __BITS(8,8), __BITS(7,3),
2392 	    CLKGATE_CON(0, 62), __BIT(13),
2393 	    0),
2394 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac",
2395 	    "clk_i2s6_8ch_tx_src",
2396 	    CLKGATE_CON(0, 62),
2397 	    RK_COMPOSITE_SET_RATE_PARENT),
2398 	RK_MUX(RK3588_CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx",
2399 	    clk_i2s6_8ch_tx_parents,
2400 	    CLKSEL_CON(0, 146), __BITS(1,0)),
2401 	RK_GATE(RK3588_MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx",
2402 	    CLKGATE_CON(0, 62), 15),
2403 	RK_COMPOSITE(RK3588_CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src",
2404 	    gpll_aupll_parents,
2405 	    CLKSEL_CON(0, 146), __BITS(7,7), __BITS(6,2),
2406 	    CLKGATE_CON(0, 63), __BIT(0),
2407 	    0),
2408 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac",
2409 	    "clk_i2s6_8ch_rx_src",
2410 	    CLKGATE_CON(0, 63),
2411 	    RK_COMPOSITE_SET_RATE_PARENT),
2412 	RK_MUX(RK3588_CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx",
2413 	    clk_i2s6_8ch_rx_parents,
2414 	    CLKSEL_CON(0, 148), __BITS(1,0)),
2415 	RK_GATE(RK3588_MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx",
2416 	    CLKGATE_CON(0, 63), 2),
2417 	RK_MUX(RK3588_I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout",
2418 	    i2s6_8ch_mclkout_parents,
2419 	    CLKSEL_CON(0, 148), __BITS(3,2)),
2420 	RK_COMPOSITE(RK3588_CLK_SPDIF3_SRC, "clk_spdif3_src",
2421 	    gpll_aupll_parents,
2422 	    CLKSEL_CON(0, 148), __BITS(9,9), __BITS(8,4),
2423 	    CLKGATE_CON(0, 63), __BIT(5),
2424 	    0),
2425 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF3_FRAC, "clk_spdif3_frac",
2426 	    "clk_spdif3_src",
2427 	    CLKGATE_CON(0, 63),
2428 	    RK_COMPOSITE_SET_RATE_PARENT),
2429 	RK_MUX(RK3588_CLK_SPDIF3, "clk_spdif3", clk_spdif3_parents,
2430 	    CLKSEL_CON(0, 150), __BITS(1,0)),
2431 	RK_GATE(RK3588_MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3",
2432 	    CLKGATE_CON(0, 63), 7),
2433 	RK_COMPOSITE(RK3588_CLK_SPDIF4_SRC, "clk_spdif4_src",
2434 	    gpll_aupll_parents,
2435 	    CLKSEL_CON(0, 150), __BITS(7,7), __BITS(6,2),
2436 	    CLKGATE_CON(0, 63), __BIT(9),
2437 	    0),
2438 	RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF4_FRAC, "clk_spdif4_frac",
2439 	    "clk_spdif4_src",
2440 	    CLKGATE_CON(0, 63),
2441 	    RK_COMPOSITE_SET_RATE_PARENT),
2442 	RK_MUX(RK3588_CLK_SPDIF4, "clk_spdif4", clk_spdif4_parents,
2443 	    CLKSEL_CON(0, 152), __BITS(1,0)),
2444 	RK_GATE(RK3588_MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4",
2445 	    CLKGATE_CON(0, 63), 11),
2446 	RK_COMPOSITE(RK3588_MCLK_SPDIFRX0, "mclk_spdifrx0",
2447 	    gpll_cpll_aupll_parents,
2448 	    CLKSEL_CON(0, 152), __BITS(8,7), __BITS(6,2),
2449 	    CLKGATE_CON(0, 63), __BIT(13),
2450 	    0),
2451 	RK_COMPOSITE(RK3588_MCLK_SPDIFRX1, "mclk_spdifrx1",
2452 	    gpll_cpll_aupll_parents,
2453 	    CLKSEL_CON(0, 152), __BITS(15,14), __BITS(13,9),
2454 	    CLKGATE_CON(0, 63), __BIT(15),
2455 	    0),
2456 	RK_COMPOSITE(RK3588_MCLK_SPDIFRX2, "mclk_spdifrx2",
2457 	    gpll_cpll_aupll_parents,
2458 	    CLKSEL_CON(0, 153), __BITS(6,5), __BITS(4,0),
2459 	    CLKGATE_CON(0, 64), __BIT(1),
2460 	    0),
2461 	RK_GATE(RK3588_CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m",
2462 	    CLKGATE_CON(0, 73), 12),
2463 	RK_GATE(RK3588_CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m",
2464 	    CLKGATE_CON(0, 73), 13),
2465 	RK_GATE(RK3588_PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root",
2466 	    CLKGATE_CON(0, 72), 5),
2467 	RK_GATE(RK3588_PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root",
2468 	    CLKGATE_CON(0, 72), 6),
2469 	RK_GATE(RK3588_PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root",
2470 	    CLKGATE_CON(0, 72), 2),
2471 	RK_GATE(RK3588_PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root",
2472 	    CLKGATE_CON(0, 72), 4),
2473 	RK_GATE(RK3588_HCLK_VOP, "hclk_vop", "hclk_vop_root",
2474 	    CLKGATE_CON(0, 52), 8),
2475 	RK_GATE(RK3588_ACLK_VOP, "aclk_vop", "aclk_vop_sub_src",
2476 	    CLKGATE_CON(0, 52), 9),
2477 	RK_COMPOSITE(RK3588_DCLK_VOP0_SRC, "dclk_vop0_src",
2478 	    gpll_cpll_v0pll_aupll_parents,
2479 	    CLKSEL_CON(0, 111), __BITS(8,7), __BITS(6,0),
2480 	    CLKGATE_CON(0, 52), __BIT(10),
2481 	    0),
2482 	RK_COMPOSITE(RK3588_DCLK_VOP1_SRC, "dclk_vop1_src",
2483 	    gpll_cpll_v0pll_aupll_parents,
2484 	    CLKSEL_CON(0, 111), __BITS(15,14), __BITS(13,9),
2485 	    CLKGATE_CON(0, 52), __BIT(11),
2486 	    0),
2487 	RK_COMPOSITE(RK3588_DCLK_VOP2_SRC, "dclk_vop2_src",
2488 	    gpll_cpll_v0pll_aupll_parents,
2489 	    CLKSEL_CON(0, 112), __BITS(6,5), __BITS(4,0),
2490 	    CLKGATE_CON(0, 52), __BIT(12),
2491 	    RK_COMPOSITE_SET_RATE_PARENT),
2492 	RK_COMPOSITE_NODIV(RK3588_DCLK_VOP0, "dclk_vop0",
2493 	    dclk_vop0_parents,
2494 	    CLKSEL_CON(0, 112), __BITS(8,7),
2495 	    CLKGATE_CON(0, 52), __BIT(13),
2496 	    RK_COMPOSITE_SET_RATE_PARENT),
2497 	RK_COMPOSITE_NODIV(RK3588_DCLK_VOP1, "dclk_vop1",
2498 	    dclk_vop1_parents,
2499 	    CLKSEL_CON(0, 112), __BITS(10,9),
2500 	    CLKGATE_CON(0, 53), __BIT(0),
2501 	    RK_COMPOSITE_SET_RATE_PARENT),
2502 	RK_COMPOSITE_NODIV(RK3588_DCLK_VOP2, "dclk_vop2",
2503 	    dclk_vop2_parents,
2504 	    CLKSEL_CON(0, 112), __BITS(12,11),
2505 	    CLKGATE_CON(0, 53), __BIT(1),
2506 	    RK_COMPOSITE_SET_RATE_PARENT),
2507 	RK_COMPOSITE(RK3588_DCLK_VOP3, "dclk_vop3",
2508 	    gpll_cpll_v0pll_aupll_parents,
2509 	    CLKSEL_CON(0, 113), __BITS(8,7), __BITS(6,0),
2510 	    CLKGATE_CON(0, 53), __BIT(2),
2511 	    0),
2512 	RK_GATE(RK3588_PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root",
2513 	    CLKGATE_CON(0, 53), 4),
2514 	RK_GATE(RK3588_PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root",
2515 	    CLKGATE_CON(0, 53), 5),
2516 	RK_COMPOSITE(RK3588_CLK_DSIHOST0, "clk_dsihost0",
2517 	    gpll_cpll_v0pll_spll_parents,
2518 	    CLKSEL_CON(0, 114), __BITS(8,7), __BITS(6,0),
2519 	    CLKGATE_CON(0, 53), __BIT(6),
2520 	    0),
2521 	RK_COMPOSITE(RK3588_CLK_DSIHOST1, "clk_dsihost1",
2522 	    gpll_cpll_v0pll_spll_parents,
2523 	    CLKSEL_CON(0, 115), __BITS(8,7), __BITS(6,0),
2524 	    CLKGATE_CON(0, 53), __BIT(7),
2525 	    0),
2526 	RK_GATE(RK3588_CLK_VOP_PMU, "clk_vop_pmu", "xin24m",
2527 	    CLKGATE_CON(0, 53), 8),
2528 	RK_GATE(RK3588_ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root",
2529 	    CLKGATE_CON(0, 53), 10),
2530 	RK_GATE(RK3588_CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal",
2531 	    "xin24m",
2532 	    CLKGATE_CON(0, 2), 8),
2533 	RK_GATE(RK3588_CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal",
2534 	    "xin24m",
2535 	    CLKGATE_CON(0, 2), 15),
2536 	RK_GATE(RK3588_CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src",
2537 	    "xin24m",
2538 	    CLKGATE_CON(0, 77), 0),
2539 	RK_GATE(RK3588_CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src",
2540 	    "xin24m",
2541 	    CLKGATE_CON(0, 77), 1),
2542 	RK_GATE(RK3588_CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src",
2543 	    "xin24m",
2544 	    CLKGATE_CON(0, 77), 2),
2545 	RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY0_PLL_SRC,
2546 	    "clk_ref_pipe_phy0_pll_src", "ppll",
2547 	    CLKSEL_CON(0, 176), __BITS(5,0),
2548 	    CLKGATE_CON(0, 77), __BIT(3),
2549 	    0),
2550 	RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY1_PLL_SRC,
2551 	    "clk_ref_pipe_phy1_pll_src", "ppll",
2552 	    CLKSEL_CON(0, 176), __BITS(11,6),
2553 	    CLKGATE_CON(0, 77), __BIT(4),
2554 	    0),
2555 	RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY2_PLL_SRC,
2556 	    "clk_ref_pipe_phy2_pll_src", "ppll",
2557 	    CLKSEL_CON(0, 177), __BITS(5,0),
2558 	    CLKGATE_CON(0, 77), __BIT(5),
2559 	    0),
2560 	RK_MUX(RK3588_CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0",
2561 	    clk_ref_pipe_phy0_parents,
2562 	    CLKSEL_CON(0, 177), __BITS(6,6)),
2563 	RK_MUX(RK3588_CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1",
2564 	    clk_ref_pipe_phy1_parents,
2565 	    CLKSEL_CON(0, 177), __BITS(7,7)),
2566 	RK_MUX(RK3588_CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2",
2567 	    clk_ref_pipe_phy2_parents,
2568 	    CLKSEL_CON(0, 177), __BITS(8,8)),
2569 	RK_COMPOSITE(RK3588_CLK_PMU1_300M_SRC, "clk_pmu1_300m_src",
2570 	    pmu_300m_24m_parents,
2571 	    CLKSEL_CON(PMU, 0), __BITS(15,15), __BITS(14,10),
2572 	    CLKGATE_CON(PMU, 0), __BIT(3),
2573 	    0),
2574 	RK_COMPOSITE(RK3588_CLK_PMU1_400M_SRC, "clk_pmu1_400m_src",
2575 	    pmu_400m_24m_parents,
2576 	    CLKSEL_CON(PMU, 1), __BITS(5,5), __BITS(4,0),
2577 	    CLKGATE_CON(PMU, 0), __BIT(4),
2578 	    0),
2579 	RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_50M_SRC, "clk_pmu1_50m_src",
2580 	    "clk_pmu1_400m_src",
2581 	    CLKSEL_CON(PMU, 0), __BITS(3,0),
2582 	    CLKGATE_CON(PMU, 0), __BIT(0),
2583 	    0),
2584 	RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_100M_SRC, "clk_pmu1_100m_src",
2585 	    "clk_pmu1_400m_src",
2586 	    CLKSEL_CON(PMU, 0), __BITS(6,4),
2587 	    CLKGATE_CON(PMU, 0), __BIT(1),
2588 	    0),
2589 	RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_200M_SRC, "clk_pmu1_200m_src",
2590 	    "clk_pmu1_400m_src",
2591 	    CLKSEL_CON(PMU, 0), __BITS(9,7),
2592 	    CLKGATE_CON(PMU, 0), __BIT(2),
2593 	    0),
2594 	RK_COMPOSITE_NODIV(RK3588_HCLK_PMU1_ROOT, "hclk_pmu1_root",
2595 	    hclk_pmu1_root_parents,
2596 	    CLKSEL_CON(PMU, 1), __BITS(7,6),
2597 	    CLKGATE_CON(PMU, 0), __BIT(5),
2598 	    0),
2599 	RK_COMPOSITE_NODIV(RK3588_PCLK_PMU1_ROOT, "pclk_pmu1_root",
2600 	    pmu_100m_50m_24m_src_parents,
2601 	    CLKSEL_CON(PMU, 1), __BITS(9,8),
2602 	    CLKGATE_CON(PMU, 0), __BIT(7),
2603 	    0),
2604 	RK_GATE(RK3588_PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root",
2605 	    CLKGATE_CON(PMU, 5), 0),
2606 	RK_COMPOSITE_NODIV(RK3588_HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root",
2607 	    hclk_pmu_cm0_root_parents,
2608 	    CLKSEL_CON(PMU, 1), __BITS(11,10),
2609 	    CLKGATE_CON(PMU, 0), __BIT(8),
2610 	    0),
2611 	RK_GATE(RK3588_CLK_PMU0, "clk_pmu0", "xin24m",
2612 	    CLKGATE_CON(PMU, 5), 1),
2613 	RK_GATE(RK3588_PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root",
2614 	    CLKGATE_CON(PMU, 5), 2),
2615 	RK_GATE(RK3588_PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root",
2616 	    CLKGATE_CON(PMU, 5), 4),
2617 	RK_GATE(RK3588_PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root",
2618 	    CLKGATE_CON(PMU, 5), 5),
2619 	RK_COMPOSITE_NODIV(RK3588_DBCLK_GPIO0, "dbclk_gpio0",
2620 	    mux_24m_32k_parents,
2621 	    CLKSEL_CON(PMU, 17), __BITS(0,0),
2622 	    CLKGATE_CON(PMU, 5), __BIT(6),
2623 	    0),
2624 	RK_GATE(RK3588_PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root",
2625 	    CLKGATE_CON(PMU, 2), 1),
2626 	RK_COMPOSITE_NODIV(RK3588_CLK_I2C0, "clk_i2c0",
2627 	    pmu_200m_100m_parents,
2628 	    CLKSEL_CON(PMU, 3), __BITS(6,6),
2629 	    CLKGATE_CON(PMU, 2), __BIT(2),
2630 	    0),
2631 	RK_GATE(RK3588_HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root",
2632 	    CLKGATE_CON(PMU, 2), 7),
2633 	RK_COMPOSITE_NOMUX(RK3588_CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src",
2634 	    "cpll",
2635 	    CLKSEL_CON(PMU, 5), __BITS(6,2),
2636 	    CLKGATE_CON(PMU, 2), __BIT(8),
2637 	    0),
2638 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac",
2639 	    "clk_i2s1_8ch_tx_src",
2640 	    CLKGATE_CON(PMU, 2),
2641 	    RK_COMPOSITE_SET_RATE_PARENT),
2642 	RK_MUX(RK3588_CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx",
2643 	    clk_i2s1_8ch_tx_parents,
2644 	    CLKSEL_CON(PMU, 7), __BITS(1,0)),
2645 	RK_GATE(RK3588_MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx",
2646 	    CLKGATE_CON(PMU, 2), 10),
2647 	RK_COMPOSITE_NOMUX(RK3588_CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src",
2648 	    "cpll",
2649 	    CLKSEL_CON(PMU, 7), __BITS(6,2),
2650 	    CLKGATE_CON(PMU, 2), __BIT(11),
2651 	    0),
2652 	RK_COMPOSITE_FRAC(RK3588_CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac",
2653 	    "clk_i2s1_8ch_rx_src",
2654 	    CLKGATE_CON(PMU, 2),
2655 	    RK_COMPOSITE_SET_RATE_PARENT),
2656 	RK_MUX(RK3588_CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx",
2657 	    clk_i2s1_8ch_rx_parents,
2658 	    CLKSEL_CON(PMU, 9), __BITS(1,0)),
2659 	RK_GATE(RK3588_MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx",
2660 	    CLKGATE_CON(PMU, 2), 13),
2661 	RK_MUX(RK3588_I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout",
2662 	    i2s1_8ch_mclkout_parents,
2663 	    CLKSEL_CON(PMU, 9), __BITS(3,2)),
2664 	RK_GATE(RK3588_PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root",
2665 	    CLKGATE_CON(PMU, 1), 0),
2666 	RK_GATE(RK3588_CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0",
2667 	    CLKGATE_CON(PMU, 1), 1),
2668 	RK_GATE(RK3588_CLK_PMU1, "clk_pmu1", "clk_pmu0",
2669 	    CLKGATE_CON(PMU, 1), 3),
2670 	RK_GATE(RK3588_HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root",
2671 	    CLKGATE_CON(PMU, 2), 14),
2672 	RK_COMPOSITE_NODIV(RK3588_MCLK_PDM0, "mclk_pdm0",
2673 	    mclk_pdm0_parents,
2674 	    CLKSEL_CON(PMU, 9), __BITS(4,4),
2675 	    CLKGATE_CON(PMU, 2), __BIT(15),
2676 	    0),
2677 	RK_GATE(RK3588_HCLK_VAD, "hclk_vad", "hclk_pmu1_root",
2678 	    CLKGATE_CON(PMU, 3), 0),
2679 	RK_GATE(RK3588_FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core",
2680 	    "hclk_pmu_cm0_root",
2681 	    CLKGATE_CON(PMU, 0), 13),
2682 	RK_COMPOSITE(RK3588_CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc",
2683 	    mux_24m_32k_parents,
2684 	    CLKSEL_CON(PMU, 2), __BITS(5,5), __BITS(4,0),
2685 	    CLKGATE_CON(PMU, 0), __BIT(15),
2686 	    0),
2687 	RK_GATE(RK3588_PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root",
2688 	    CLKGATE_CON(PMU, 1), 5),
2689 	RK_GATE(RK3588_PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root",
2690 	    CLKGATE_CON(PMU, 1), 12),
2691 	RK_COMPOSITE_NODIV(RK3588_CLK_PMU1PWM, "clk_pmu1pwm",
2692 	    pmu_100m_50m_24m_src_parents,
2693 	    CLKSEL_CON(PMU, 2), __BITS(10,9),
2694 	    CLKGATE_CON(PMU, 1), __BIT(13),
2695 	    0),
2696 	RK_GATE(RK3588_CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m",
2697 	    CLKGATE_CON(PMU, 1), 14),
2698 	RK_GATE(RK3588_PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root",
2699 	    CLKGATE_CON(PMU, 1), 8),
2700 	RK_COMPOSITE_NODIV(RK3588_CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root",
2701 	    pmu_24m_32k_100m_src_parents,
2702 	    CLKSEL_CON(PMU, 2), __BITS(8,7),
2703 	    CLKGATE_CON(PMU, 1), __BIT(9),
2704 	    0),
2705 	RK_GATE(RK3588_CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root",
2706 	    CLKGATE_CON(PMU, 1), 10),
2707 	RK_GATE(RK3588_CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root",
2708 	    CLKGATE_CON(PMU, 1), 11),
2709 	RK_COMPOSITE_NOMUX(RK3588_CLK_UART0_SRC, "clk_uart0_src", "cpll",
2710 	    CLKSEL_CON(PMU, 3), __BITS(11,7),
2711 	    CLKGATE_CON(PMU, 2), __BIT(3),
2712 	    0),
2713 	RK_COMPOSITE_FRAC(RK3588_CLK_UART0_FRAC, "clk_uart0_frac",
2714 	    "clk_uart0_src",
2715 	    CLKGATE_CON(PMU, 2),
2716 	    RK_COMPOSITE_SET_RATE_PARENT),
2717 	RK_MUX(RK3588_CLK_UART0, "clk_uart0", clk_uart0_parents,
2718 	    CLKSEL_CON(PMU, 5), __BITS(1,0)),
2719 	RK_GATE(RK3588_SCLK_UART0, "sclk_uart0", "clk_uart0",
2720 	    CLKGATE_CON(PMU, 2), 5),
2721 	RK_GATE(RK3588_PCLK_UART0, "pclk_uart0", "pclk_pmu0_root",
2722 	    CLKGATE_CON(PMU, 2), 6),
2723 	RK_GATE(RK3588_PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root",
2724 	    CLKGATE_CON(PMU, 1), 6),
2725 	RK_COMPOSITE_NODIV(RK3588_TCLK_PMU1WDT, "tclk_pmu1wdt",
2726 	    mux_24m_32k_parents,
2727 	    CLKSEL_CON(PMU, 2), __BITS(6,6),
2728 	    CLKGATE_CON(PMU, 1), __BIT(7),
2729 	    0),
2730 	RK_COMPOSITE(RK3588_CLK_CR_PARA, "clk_cr_para",
2731 	    mux_24m_ppll_spll_parents,
2732 	    CLKSEL_CON(PMU, 15), __BITS(6,5), __BITS(4,0),
2733 	    CLKGATE_CON(PMU, 4), __BIT(11),
2734 	    0),
2735 	RK_COMPOSITE(RK3588_CLK_USB2PHY_HDPTXRXPHY_REF,
2736 	    "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_parents,
2737 	    CLKSEL_CON(PMU, 14), __BITS(14,14), __BITS(13,9),
2738 	    CLKGATE_CON(PMU, 4), __BIT(7),
2739 	    0),
2740 	RK_COMPOSITE(RK3588_CLK_USBDPPHY_MIPIDCPPHY_REF,
2741 	    "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_parents,
2742 	    CLKSEL_CON(PMU, 14), __BITS(8,7), __BITS(6,0),
2743 	    CLKGATE_CON(PMU, 4), __BIT(3),
2744 	    0),
2745 	RK_GATE(RK3588_CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll",
2746 	    RK3588_PHYREF_ALT_GATE, 0),
2747 	RK_GATE(RK3588_CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll",
2748 	    RK3588_PHYREF_ALT_GATE, 1),
2749 	RK_GATE(RK3588_CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll",
2750 	    RK3588_PHYREF_ALT_GATE, 2),
2751 	RK_GATE(RK3588_CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll",
2752 	    RK3588_PHYREF_ALT_GATE, 3),
2753 	RK_GATE(RK3588_HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1",
2754 	    CLKGATE_CON(0, 63), 12),
2755 	RK_GATE(RK3588_HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1",
2756 	    CLKGATE_CON(0, 63), 14),
2757 	RK_GATE(RK3588_HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1",
2758 	    CLKGATE_CON(0, 64), 0),
2759 	RK_GATE(RK3588_HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1",
2760 	    CLKGATE_CON(0, 63), 8),
2761 	RK_GATE(RK3588_HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1",
2762 	    CLKGATE_CON(0, 63), 4),
2763 	RK_GATE(RK3588_HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1",
2764 	    CLKGATE_CON(0, 63), 3),
2765 	RK_GATE(RK3588_HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1",
2766 	    CLKGATE_CON(0, 62), 12),
2767 	RK_GATE(RK3588_HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1",
2768 	    CLKGATE_CON(0, 65), 0),
2769 	RK_GATE(RK3588_HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1",
2770 	    CLKGATE_CON(0, 60), 0),
2771 	RK_GATE(RK3588_HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1",
2772 	    CLKGATE_CON(0, 65), 4),
2773 	RK_GATE(RK3588_ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre",
2774 	    CLKGATE_CON(0, 60), 5),
2775 	RK_GATE(RK3588_HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1",
2776 	    CLKGATE_CON(0, 60), 6),
2777 	RK_GATE(RK3588_HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0",
2778 	    CLKGATE_CON(0, 57), 7),
2779 	RK_GATE(RK3588_HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0",
2780 	    CLKGATE_CON(0, 57), 2),
2781 	RK_GATE(RK3588_HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0",
2782 	    CLKGATE_CON(0, 56), 14),
2783 	RK_GATE(RK3588_HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0",
2784 	    CLKGATE_CON(0, 56), 10),
2785 	RK_GATE(RK3588_ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre",
2786 	    CLKGATE_CON(0, 55), 12),
2787 	RK_GATE(RK3588_HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0",
2788 	    CLKGATE_CON(0, 55), 13),
2789 	RK_GATE(RK3588_HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre",
2790 	    CLKGATE_CON(0, 48), 4),
2791 	RK_GATE(RK3588_ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre",
2792 	    CLKGATE_CON(0, 48), 5),
2793 	RK_GATE(RK3588_ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre",
2794 	    CLKGATE_CON(0, 44), 8),
2795 	RK_GATE(RK3588_ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre",
2796 	    CLKGATE_CON(0, 45), 5),
2797 	RK_GATE(RK3588_ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0",
2798 	    "aclk_vdpu_low_pre",
2799 	    CLKGATE_CON(0, 44), 10),
2800 	RK_GATE(RK3588_ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1",
2801 	    "aclk_vdpu_low_pre",
2802 	    CLKGATE_CON(0, 44), 12),
2803 	RK_GATE(RK3588_ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2",
2804 	    "aclk_vdpu_low_pre",
2805 	    CLKGATE_CON(0, 44), 14),
2806 	RK_GATE(RK3588_ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3",
2807 	    "aclk_vdpu_low_pre",
2808 	    CLKGATE_CON(0, 45), 0),
2809 	RK_GATE(RK3588_ACLK_JPEG_DECODER, "aclk_jpeg_decoder",
2810 	    "aclk_jpeg_decoder_pre",
2811 	    CLKGATE_CON(0, 45), 2),
2812 	RK_GATE(RK3588_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb",
2813 	    CLKGATE_CON(0, 42), 7),
2814 	RK_GATE(RK3588_HCLK_HOST0, "hclk_host0", "hclk_usb",
2815 	    CLKGATE_CON(0, 42), 10),
2816 	RK_GATE(RK3588_HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb",
2817 	    CLKGATE_CON(0, 42), 11),
2818 	RK_GATE(RK3588_HCLK_HOST1, "hclk_host1", "hclk_usb",
2819 	    CLKGATE_CON(0, 42), 12),
2820 	RK_GATE(RK3588_HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb",
2821 	    CLKGATE_CON(0, 42), 13),
2822 	RK_GATE(RK3588_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb",
2823 	    CLKGATE_CON(0, 42), 4),
2824 	RK_GATE(RK3588_HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre",
2825 	    CLKGATE_CON(0, 75), 2),
2826 	RK_GATE(RK3588_HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre",
2827 	    CLKGATE_CON(0, 41), 2),
2828 	RK_GATE(RK3588_ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre",
2829 	    CLKGATE_CON(0, 41), 3),
2830 	RK_GATE(RK3588_HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre",
2831 	    CLKGATE_CON(0, 40), 3),
2832 	RK_GATE(RK3588_ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre",
2833 	    CLKGATE_CON(0, 40), 4),
2834 	RK_GATE(RK3588_CLK_PCIE4L_PIPE, "clk_pcie4l_pipe",
2835 	    "clk_pipe30phy_pipe0_i",
2836 	    CLKGATE_CON(0, 39), 0),
2837 	RK_GATE(RK3588_CLK_PCIE2L_PIPE, "clk_pcie2l_pipe",
2838 	    "clk_pipe30phy_pipe2_i",
2839 	    CLKGATE_CON(0, 39), 1),
2840 	RK_GATE(RK3588_CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g",
2841 	    "clk_pipephy0_pipe_i",
2842 	    CLKGATE_CON(0, 38), 3),
2843 	RK_GATE(RK3588_CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g",
2844 	    "clk_pipephy1_pipe_i",
2845 	    CLKGATE_CON(0, 38), 4),
2846 	RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g",
2847 	    "clk_pipephy2_pipe_i",
2848 	    CLKGATE_CON(0, 38), 5),
2849 	RK_GATE(RK3588_CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g",
2850 	    "clk_pipephy0_pipe_i",
2851 	    CLKGATE_CON(0, 38), 6),
2852 	RK_GATE(RK3588_CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g",
2853 	    "clk_pipephy1_pipe_i",
2854 	    CLKGATE_CON(0, 38), 7),
2855 	RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g",
2856 	    "clk_pipephy2_pipe_i",
2857 	    CLKGATE_CON(0, 38), 8),
2858 	RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g",
2859 	    "clk_pipephy2_pipe_i",
2860 	    CLKGATE_CON(0, 38), 9),
2861 	RK_GATE(RK3588_CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe",
2862 	    "clk_pipephy0_pipe_g",
2863 	    CLKGATE_CON(0, 38), 13),
2864 	RK_GATE(RK3588_CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe",
2865 	    "clk_pipephy1_pipe_g",
2866 	    CLKGATE_CON(0, 38), 14),
2867 	RK_GATE(RK3588_CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe",
2868 	    "clk_pipephy2_pipe_g",
2869 	    CLKGATE_CON(0, 38), 15),
2870 	RK_GATE(RK3588_HCLK_SFC, "hclk_sfc", "hclk_nvm",
2871 	    CLKGATE_CON(0, 31), 10),
2872 	RK_GATE(RK3588_HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm",
2873 	    CLKGATE_CON(0, 31), 11),
2874 	RK_GATE(RK3588_HCLK_EMMC, "hclk_emmc", "hclk_nvm",
2875 	    CLKGATE_CON(0, 31), 4),
2876 	RK_GATE(RK3588_ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre",
2877 	    CLKGATE_CON(0, 26), 5),
2878 	RK_GATE(RK3588_HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre",
2879 	    CLKGATE_CON(0, 26), 7),
2880 	RK_GATE(RK3588_PCLK_AV1, "pclk_av1", "pclk_av1_pre",
2881 	    CLKGATE_CON(0, 68), 5),
2882 	RK_GATE(RK3588_ACLK_AV1, "aclk_av1", "aclk_av1_pre",
2883 	    CLKGATE_CON(0, 68), 2),
2884 
2885 #if 0
2886 	notyet
2887 #define RK3588_SDIO_CON0		0x0c24
2888 #define RK3588_SDIO_CON1		0x0c28
2889 #define RK3588_SDMMC_CON0		0x0c30
2890 #define RK3588_SDMMC_CON1		0x0c34
2891 	SCLK_SDIO_DRV, "sdio_drv","cclk_src_sdio", RK3588_SDIO_CON0
2892 	SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1
2893 	SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0
2894 	SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1
2895 #endif
2896 
2897 };
2898 
2899 static void
rk3588_cru_init(struct rk_cru_softc * sc)2900 rk3588_cru_init(struct rk_cru_softc *sc)
2901 {
2902 }
2903 
2904 static int
rk3588_cru_match(device_t parent,cfdata_t cf,void * aux)2905 rk3588_cru_match(device_t parent, cfdata_t cf, void *aux)
2906 {
2907 	struct fdt_attach_args * const faa = aux;
2908 	return of_compatible_match(faa->faa_phandle, compat_data);
2909 }
2910 
2911 static void
rk3588_cru_attach(device_t parent,device_t self,void * aux)2912 rk3588_cru_attach(device_t parent, device_t self, void *aux)
2913 {
2914 	struct rk_cru_softc * const sc = device_private(self);
2915 	struct fdt_attach_args * const faa = aux;
2916 
2917 	sc->sc_dev = self;
2918 	sc->sc_phandle = faa->faa_phandle;
2919 	sc->sc_bst = faa->faa_bst;
2920 	sc->sc_clks = rk3588_cru_clks;
2921 	sc->sc_nclks = __arraycount(rk3588_cru_clks);
2922 
2923 	sc->sc_grf_soc_status = 0x0480;	/* XXX */
2924 	sc->sc_softrst_base = SOFTRST_CON(0, 0);	/* XXX */
2925 
2926 	if (rk_cru_attach(sc) != 0)
2927 		return;
2928 
2929 	aprint_naive("\n");
2930 	aprint_normal(": RK3588 CRU\n");
2931 
2932 	rk3588_cru_init(sc);
2933 
2934 	rk_cru_print(sc);
2935 }
2936