1 /* $NetBSD: rk3399_pmucru.h,v 1.1 2018/08/12 16:48:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _RK3399_PMUCRU_H 30 #define _RK3399_PMUCRU_H 31 32 /* 33 * Clocks 34 */ 35 36 #define RK3399_PLL_PPLL 1 37 #define RK3399_SCLK_32K_SUSPEND_PMU 2 38 #define RK3399_SCLK_SPI3_PMU 3 39 #define RK3399_SCLK_TIMER12_PMU 4 40 #define RK3399_SCLK_TIMER13_PMU 5 41 #define RK3399_SCLK_UART4_PMU 6 42 #define RK3399_SCLK_PVTM_PMU 7 43 #define RK3399_SCLK_WIFI_PMU 8 44 #define RK3399_SCLK_I2C0_PMU 9 45 #define RK3399_SCLK_I2C4_PMU 10 46 #define RK3399_SCLK_I2C8_PMU 11 47 #define RK3399_PCLK_SRC_PMU 19 48 #define RK3399_PCLK_PMU 20 49 #define RK3399_PCLK_PMUGRF_PMU 21 50 #define RK3399_PCLK_INTMEM1_PMU 22 51 #define RK3399_PCLK_GPIO0_PMU 23 52 #define RK3399_PCLK_GPIO1_PMU 24 53 #define RK3399_PCLK_SGRF_PMU 25 54 #define RK3399_PCLK_NOC_PMU 26 55 #define RK3399_PCLK_I2C0_PMU 27 56 #define RK3399_PCLK_I2C4_PMU 28 57 #define RK3399_PCLK_I2C8_PMU 29 58 #define RK3399_PCLK_RKPWM_PMU 30 59 #define RK3399_PCLK_SPI3_PMU 31 60 #define RK3399_PCLK_TIMER_PMU 32 61 #define RK3399_PCLK_MAILBOX_PMU 33 62 #define RK3399_PCLK_UART4_PMU 34 63 #define RK3399_PCLK_WDT_M0_PMU 35 64 #define RK3399_FCLK_CM0S_SRC_PMU 44 65 #define RK3399_FCLK_CM0S_PMU 45 66 #define RK3399_SCLK_CM0S_PMU 46 67 #define RK3399_HCLK_CM0S_PMU 47 68 #define RK3399_DCLK_CM0S_PMU 48 69 #define RK3399_PCLK_INTR_ARB_PMU 49 70 #define RK3399_HCLK_NOC_PMU 50 71 72 #endif /* !_RK3399_PMUCRU_H */ 73