1 /* $NetBSD: rk3328_iomux.c,v 1.8 2021/08/07 16:18:45 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk3328_iomux.c,v 1.8 2021/08/07 16:18:45 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/mutex.h>
38 #include <sys/kmem.h>
39 #include <sys/lwp.h>
40
41 #include <dev/fdt/fdtvar.h>
42 #include <dev/fdt/syscon.h>
43
44 #define GRF_GPIO_P_REG(_bank, _idx) (0x0100 + (_bank) * 0x10 + ((_idx) >> 3) * 4)
45 #define GRF_GPIO_P_CTL(_idx) (0x3 << (((_idx) & 7) * 2))
46 #define GRF_GPIO_P_CTL_Z 0
47 #define GRF_GPIO_P_CTL_PULLUP 1
48 #define GRF_GPIO_P_CTL_PULLDOWN 2
49 #define GRF_GPIO_P_CTL_REPEATER 3
50 #define GRF_GPIO_P_CTL_MASK 0x3
51 #define GRF_GPIO_P_WRITE_EN(_idx) (0x3 << (((_idx) & 7) * 2 + 16))
52
53 #define GRF_GPIO_E_REG(_bank, _idx) (0x0200 + (_bank) * 0x10 + ((_idx) >> 3) * 4)
54 #define GRF_GPIO_E_CTL(_idx) (0x3 << (((_idx) & 7) * 2))
55 #define GRF_GPIO_E_CTL_2MA 0
56 #define GRF_GPIO_E_CTL_4MA 1
57 #define GRF_GPIO_E_CTL_8MA 2
58 #define GRF_GPIO_E_CTL_12MA 3
59 #define GRF_GPIO_E_CTL_MASK 0x3
60 #define GRF_GPIO_E_WRITE_EN(_idx) (0x3 << (((_idx) & 7) * 2 + 16))
61
62 struct rk3328_iomux {
63 bus_size_t base;
64 u_int type;
65 #define RK3328_IOMUX_TYPE_3BIT 0x01
66 };
67
68 struct rk3328_iomux_bank {
69 struct rk3328_iomux iomux[4];
70 };
71
72 static const struct rk3328_iomux_bank rk3328_iomux_banks[] = {
73 [0] = {
74 .iomux = {
75 [0] = { .base = 0x0000 },
76 [1] = { .base = 0x0004 },
77 [2] = { .base = 0x0008 },
78 [3] = { .base = 0x000c },
79 },
80 },
81 [1] = {
82 .iomux = {
83 [0] = { .base = 0x0010 },
84 [1] = { .base = 0x0014 },
85 [2] = { .base = 0x0018 },
86 [3] = { .base = 0x001c },
87 }
88 },
89 [2] = {
90 .iomux = {
91 [0] = { .base = 0x0020 },
92 [1] = { .base = 0x0024, .type = RK3328_IOMUX_TYPE_3BIT },
93 [2] = { .base = 0x002c, .type = RK3328_IOMUX_TYPE_3BIT },
94 [3] = { .base = 0x0034 },
95 },
96 },
97 [3] = {
98 .iomux = {
99 [0] = { .base = 0x0038, .type = RK3328_IOMUX_TYPE_3BIT },
100 [1] = { .base = 0x0040, .type = RK3328_IOMUX_TYPE_3BIT },
101 [2] = { .base = 0x0048 },
102 [3] = { .base = 0x004c },
103 },
104 },
105 };
106
107 struct rk3328_iomux_conf {
108 const struct rk3328_iomux_bank *banks;
109 u_int nbanks;
110 };
111
112 static const struct rk3328_iomux_conf rk3328_iomux_conf = {
113 .banks = rk3328_iomux_banks,
114 .nbanks = __arraycount(rk3328_iomux_banks),
115 };
116
117 static const struct device_compatible_entry compat_data[] = {
118 { .compat = "rockchip,rk3328-pinctrl", .data = &rk3328_iomux_conf },
119 DEVICE_COMPAT_EOL
120 };
121
122 struct rk3328_iomux_softc {
123 device_t sc_dev;
124 struct syscon *sc_syscon;
125
126 const struct rk3328_iomux_conf *sc_conf;
127 };
128
129 #define LOCK(sc) \
130 syscon_lock((sc)->sc_syscon)
131 #define UNLOCK(sc) \
132 syscon_unlock((sc)->sc_syscon)
133 #define RD4(sc, reg) \
134 syscon_read_4((sc)->sc_syscon, (reg))
135 #define WR4(sc, reg, val) \
136 syscon_write_4((sc)->sc_syscon, (reg), (val))
137
138 static int rk3328_iomux_match(device_t, cfdata_t, void *);
139 static void rk3328_iomux_attach(device_t, device_t, void *);
140
141 CFATTACH_DECL_NEW(rk3328_iomux, sizeof(struct rk3328_iomux_softc),
142 rk3328_iomux_match, rk3328_iomux_attach, NULL, NULL);
143
144 static void
rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc * sc,u_int bank,u_int pin,bus_size_t * reg,uint32_t * mask)145 rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)
146 {
147 const struct rk3328_iomux_bank *banks = sc->sc_conf->banks;
148
149 KASSERT(bank < sc->sc_conf->nbanks);
150
151 *reg = banks[bank].iomux[pin / 8].base;
152 if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
153 if ((pin % 8) >= 5)
154 *reg += 0x04;
155 const u_int bit = (pin % 8 % 5) * 3;
156 *mask = 7 << bit;
157 } else {
158 const u_int bit = (pin % 8) * 2;
159 *mask = 3 << bit;
160 }
161 }
162
163 static void
rk3328_iomux_set_bias(struct rk3328_iomux_softc * sc,u_int bank,u_int idx,u_int bias)164 rk3328_iomux_set_bias(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int bias)
165 {
166 WR4(sc, GRF_GPIO_P_REG(bank, idx),
167 __SHIFTIN(GRF_GPIO_P_CTL_MASK, GRF_GPIO_P_WRITE_EN(idx)) |
168 __SHIFTIN(bias, GRF_GPIO_P_CTL(idx)));
169 }
170
171 static void
rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc * sc,u_int bank,u_int idx,u_int drv)172 rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int drv)
173 {
174 WR4(sc, GRF_GPIO_E_REG(bank, idx),
175 __SHIFTIN(GRF_GPIO_E_CTL_MASK, GRF_GPIO_E_WRITE_EN(idx)) |
176 __SHIFTIN(drv, GRF_GPIO_E_CTL(idx)));
177 }
178
179 static void
rk3328_iomux_set_mux(struct rk3328_iomux_softc * sc,u_int bank,u_int idx,u_int mux)180 rk3328_iomux_set_mux(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
181 {
182 bus_size_t reg;
183 uint32_t mask;
184
185 rk3328_iomux_calc_iomux_reg(sc, bank, idx, ®, &mask);
186
187 WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));
188 }
189
190 static int
rk3328_iomux_config(struct rk3328_iomux_softc * sc,const int phandle,u_int bank,u_int idx,u_int mux)191 rk3328_iomux_config(struct rk3328_iomux_softc *sc, const int phandle, u_int bank, u_int idx, u_int mux)
192 {
193
194 const int bias = fdtbus_pinctrl_parse_bias(phandle, NULL);
195 switch (bias) {
196 case 0:
197 rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_Z);
198 break;
199 case GPIO_PIN_PULLUP:
200 rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_PULLUP);
201 break;
202 case GPIO_PIN_PULLDOWN:
203 rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_PULLDOWN);
204 break;
205 }
206
207 const int drv = fdtbus_pinctrl_parse_drive_strength(phandle);
208 switch (drv) {
209 case -1:
210 break;
211 case 2:
212 rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_2MA);
213 break;
214 case 4:
215 rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_4MA);
216 break;
217 case 8:
218 rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_8MA);
219 break;
220 case 12:
221 rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_12MA);
222 break;
223 default:
224 aprint_error_dev(sc->sc_dev, "unsupported drive-strength %u\n", drv);
225 return EINVAL;
226 }
227
228 #if notyet
229 int output_value;
230 const int direction =
231 fdtbus_pinctrl_parse_input_output(phandle, &output_value);
232 if (direction != -1) {
233 rk3328_iomux_set_direction(sc, bank, idx, direction,
234 output_value);
235 }
236 #endif
237
238 rk3328_iomux_set_mux(sc, bank, idx, mux);
239
240 return 0;
241 }
242
243 static int
rk3328_iomux_pinctrl_set_config(device_t dev,const void * data,size_t len)244 rk3328_iomux_pinctrl_set_config(device_t dev, const void *data, size_t len)
245 {
246 struct rk3328_iomux_softc * const sc = device_private(dev);
247 int pins_len;
248
249 if (len != 4)
250 return -1;
251
252 const int phandle = fdtbus_get_phandle_from_native(be32dec(data));
253 const u_int *pins = fdtbus_get_prop(phandle, "rockchip,pins", &pins_len);
254
255 while (pins_len >= 16) {
256 const u_int bank = be32toh(pins[0]);
257 const u_int idx = be32toh(pins[1]);
258 const u_int mux = be32toh(pins[2]);
259 const int cfg = fdtbus_get_phandle_from_native(be32toh(pins[3]));
260
261 LOCK(sc);
262 rk3328_iomux_config(sc, cfg, bank, idx, mux);
263 UNLOCK(sc);
264
265 pins_len -= 16;
266 pins += 4;
267 }
268
269 return 0;
270 }
271
272 static struct fdtbus_pinctrl_controller_func rk3328_iomux_pinctrl_funcs = {
273 .set_config = rk3328_iomux_pinctrl_set_config,
274 };
275
276 static int
rk3328_iomux_match(device_t parent,cfdata_t cf,void * aux)277 rk3328_iomux_match(device_t parent, cfdata_t cf, void *aux)
278 {
279 struct fdt_attach_args * const faa = aux;
280
281 return of_compatible_match(faa->faa_phandle, compat_data);
282 }
283
284 static void
rk3328_iomux_attach(device_t parent,device_t self,void * aux)285 rk3328_iomux_attach(device_t parent, device_t self, void *aux)
286 {
287 struct rk3328_iomux_softc * const sc = device_private(self);
288 struct fdt_attach_args * const faa = aux;
289 const int phandle = faa->faa_phandle;
290 int child, sub;
291
292 sc->sc_dev = self;
293 sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf");
294 if (sc->sc_syscon == NULL) {
295 aprint_error(": couldn't acquire grf syscon\n");
296 return;
297 }
298 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data;
299
300 aprint_naive("\n");
301 aprint_normal(": RK3328 IOMUX control\n");
302
303 for (child = OF_child(phandle); child; child = OF_peer(child)) {
304 for (sub = OF_child(child); sub; sub = OF_peer(sub)) {
305 if (!of_hasprop(sub, "rockchip,pins"))
306 continue;
307 fdtbus_register_pinctrl_config(self, sub, &rk3328_iomux_pinctrl_funcs);
308 }
309 }
310
311 for (child = OF_child(phandle); child; child = OF_peer(child)) {
312 struct fdt_attach_args cfaa = *faa;
313 cfaa.faa_phandle = child;
314 cfaa.faa_name = fdtbus_get_string(child, "name");
315 cfaa.faa_quiet = false;
316
317 config_found(self, &cfaa, NULL, CFARGS_NONE);
318 }
319 }
320