1 /* $NetBSD: tegra_var.h,v 1.46 2019/01/31 13:06:10 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef _ARM_TEGRA_VAR_H
30 #define _ARM_TEGRA_VAR_H
31
32 #include <sys/types.h>
33 #include <sys/bus.h>
34 #include <sys/gpio.h>
35
36 #include "opt_tegra.h"
37
38 extern struct bus_space arm_generic_bs_tag;
39 extern struct bus_space arm_generic_a4x_bs_tag;
40 extern bus_space_handle_t tegra_ppsb_bsh;
41 extern bus_space_handle_t tegra_apb_bsh;
42
43 void tegra_bootstrap(void);
44
45 struct tegra_gpio_pin;
46 struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
47 void tegra_gpio_release(struct tegra_gpio_pin *);
48 int tegra_gpio_read(struct tegra_gpio_pin *);
49 void tegra_gpio_write(struct tegra_gpio_pin *, int);
50
51 void tegra_pmc_reset(void);
52 void tegra_pmc_power(u_int, bool);
53 void tegra_pmc_remove_clamping(u_int);
54 void tegra_pmc_hdmi_enable(void);
55
56 void tegra210_car_xusbio_enable_hw_control(void);
57 void tegra210_car_xusbio_enable_hw_seq(void);
58 void tegra210_car_sata_enable_hw_control(void);
59 void tegra210_car_sata_enable_hw_seq(void);
60
61 uint32_t tegra_fuse_read(u_int);
62
63 void tegra_timer_delay(u_int);
64
65 struct videomode;
66 int tegra_dc_port(device_t);
67 int tegra_dc_enable(device_t, device_t, const struct videomode *,
68 const uint8_t *);
69 void tegra_dc_hdmi_start(device_t);
70
71 #define TEGRA_CPUFREQ_MAX 16
72 struct tegra_cpufreq_func {
73 u_int (*set_rate)(u_int);
74 u_int (*get_rate)(void);
75 size_t (*get_available)(u_int *, size_t);
76 };
77 void tegra_cpufreq_register(const struct tegra_cpufreq_func *);
78
79 #if defined(SOC_TEGRA124)
80 int tegra124_mpstart(void);
81 #endif
82
83 static void inline
tegra_reg_set_clear(bus_space_tag_t bst,bus_space_handle_t bsh,bus_size_t o,uint32_t set_mask,uint32_t clr_mask)84 tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
85 bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
86 {
87 const uint32_t old = bus_space_read_4(bst, bsh, o);
88 const uint32_t new = set_mask | (old & ~clr_mask);
89 if (old != new) {
90 bus_space_write_4(bst, bsh, o, new);
91 }
92 }
93
94 #endif /* _ARM_TEGRA_VAR_H */
95