xref: /netbsd-src/sys/arch/arm/nvidia/tegra_sdhc.c (revision d909946ca08dceb44d7d0f22ec9488679695d976)
1 /* $NetBSD: tegra_sdhc.c,v 1.15 2015/12/22 22:10:36 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include "locators.h"
30 
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.15 2015/12/22 22:10:36 jmcneill Exp $");
33 
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 
41 #include <dev/sdmmc/sdhcreg.h>
42 #include <dev/sdmmc/sdhcvar.h>
43 #include <dev/sdmmc/sdmmcvar.h>
44 
45 #include <arm/nvidia/tegra_reg.h>
46 #include <arm/nvidia/tegra_var.h>
47 
48 #include <dev/fdt/fdtvar.h>
49 
50 static int	tegra_sdhc_match(device_t, cfdata_t, void *);
51 static void	tegra_sdhc_attach(device_t, device_t, void *);
52 
53 static int	tegra_sdhc_card_detect(struct sdhc_softc *);
54 static int	tegra_sdhc_write_protect(struct sdhc_softc *);
55 
56 struct tegra_sdhc_softc {
57 	struct sdhc_softc	sc;
58 
59 	struct clk		*sc_clk;
60 	struct fdtbus_reset	*sc_rst;
61 
62 	bus_space_tag_t		sc_bst;
63 	bus_space_handle_t	sc_bsh;
64 	bus_size_t		sc_bsz;
65 	struct sdhc_host	*sc_host;
66 	void			*sc_ih;
67 
68 	struct fdtbus_gpio_pin	*sc_pin_cd;
69 	struct fdtbus_gpio_pin	*sc_pin_power;
70 	struct fdtbus_gpio_pin	*sc_pin_wp;
71 };
72 
73 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc),
74 	tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL);
75 
76 static int
77 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux)
78 {
79 	const char * const compatible[] = { "nvidia,tegra124-sdhci", NULL };
80 	struct fdt_attach_args * const faa = aux;
81 
82 	return of_match_compatible(faa->faa_phandle, compatible);
83 }
84 
85 static void
86 tegra_sdhc_attach(device_t parent, device_t self, void *aux)
87 {
88 	struct tegra_sdhc_softc * const sc = device_private(self);
89 	struct fdt_attach_args * const faa = aux;
90 	char intrstr[128];
91 	bus_addr_t addr;
92 	bus_size_t size;
93 	u_int bus_width;
94 	int error;
95 
96 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
97 		aprint_error(": couldn't get registers\n");
98 		return;
99 	}
100 
101 	if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width))
102 		bus_width = 4;
103 
104 	sc->sc.sc_dev = self;
105 	sc->sc.sc_dmat = faa->faa_dmat;
106 	sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS |
107 			  SDHC_FLAG_NO_PWR0 |
108 			  SDHC_FLAG_NO_CLKBASE |
109 			  SDHC_FLAG_NO_TIMEOUT |
110 			  SDHC_FLAG_SINGLE_POWER_WRITE |
111 			  SDHC_FLAG_USE_DMA |
112 			  SDHC_FLAG_USE_ADMA2;
113 	if (bus_width == 8) {
114 		sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
115 	}
116 	sc->sc.sc_host = &sc->sc_host;
117 
118 	sc->sc_bst = faa->faa_bst;
119 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
120 	if (error) {
121 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
122 		return;
123 	}
124 	sc->sc_bsz = size;
125 
126 	sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle,
127 	    "power-gpios", GPIO_PIN_OUTPUT);
128 	if (sc->sc_pin_power)
129 		fdtbus_gpio_write(sc->sc_pin_power, 1);
130 
131 	sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle,
132 	    "cd-gpios", GPIO_PIN_INPUT);
133 	sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle,
134 	    "wp-gpios", GPIO_PIN_INPUT);
135 
136 	if (sc->sc_pin_cd) {
137 		sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect;
138 		sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET;
139 	}
140 	if (sc->sc_pin_wp) {
141 		sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect;
142 	}
143 
144 	sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
145 	if (sc->sc_clk == NULL) {
146 		aprint_error(": couldn't get clock\n");
147 		return;
148 	}
149 	sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci");
150 	if (sc->sc_rst == NULL) {
151 		aprint_error(": couldn't get reset\n");
152 		return;
153 	}
154 
155 	fdtbus_reset_assert(sc->sc_rst);
156 	error = clk_set_rate(sc->sc_clk, 204000000);
157 	if (error) {
158 		aprint_error(": couldn't set frequency: %d\n", error);
159 		return;
160 	}
161 	error = clk_enable(sc->sc_clk);
162 	if (error) {
163 		aprint_error(": couldn't enable clock: %d\n", error);
164 		return;
165 	}
166 	fdtbus_reset_deassert(sc->sc_rst);
167 
168 	sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
169 
170 	aprint_naive("\n");
171 	aprint_normal(": SDMMC\n");
172 
173 	if (sc->sc.sc_clkbase == 0) {
174 		aprint_error_dev(self, "couldn't determine frequency\n");
175 		return;
176 	}
177 
178 	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
179 		aprint_error_dev(self, "failed to decode interrupt\n");
180 		return;
181 	}
182 
183 	sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0,
184 	    sdhc_intr, &sc->sc);
185 	if (sc->sc_ih == NULL) {
186 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
187 		    intrstr);
188 		return;
189 	}
190 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
191 
192 	error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
193 	if (error) {
194 		aprint_error_dev(self, "couldn't initialize host, error = %d\n",
195 		    error);
196 		fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih);
197 		sc->sc_ih = NULL;
198 		return;
199 	}
200 }
201 
202 static int
203 tegra_sdhc_card_detect(struct sdhc_softc *ssc)
204 {
205 	struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
206 
207 	KASSERT(sc->sc_pin_cd != NULL);
208 
209 	return fdtbus_gpio_read(sc->sc_pin_cd);
210 }
211 
212 static int
213 tegra_sdhc_write_protect(struct sdhc_softc *ssc)
214 {
215 	struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
216 
217 	KASSERT(sc->sc_pin_wp != NULL);
218 
219 	return fdtbus_gpio_read(sc->sc_pin_wp);
220 }
221