1 /* $NetBSD: tegra_sdhc.c,v 1.32 2022/02/06 15:52:20 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #define TEGRA_SDHC_NO_SDR104
30
31 #include "locators.h"
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.32 2022/02/06 15:52:20 jmcneill Exp $");
35
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/device.h>
39 #include <sys/intr.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42
43 #include <dev/sdmmc/sdhcreg.h>
44 #include <dev/sdmmc/sdhcvar.h>
45 #include <dev/sdmmc/sdmmcvar.h>
46
47 #include <arm/nvidia/tegra_reg.h>
48 #include <arm/nvidia/tegra_var.h>
49
50 #include <dev/fdt/fdtvar.h>
51
52 static int tegra_sdhc_match(device_t, cfdata_t, void *);
53 static void tegra_sdhc_attach(device_t, device_t, void *);
54
55 static int tegra_sdhc_card_detect(struct sdhc_softc *);
56 static int tegra_sdhc_write_protect(struct sdhc_softc *);
57 static int tegra_sdhc_signal_voltage(struct sdhc_softc *, int);
58
59 struct tegra_sdhc_softc {
60 struct sdhc_softc sc;
61
62 struct clk *sc_clk;
63 struct fdtbus_reset *sc_rst;
64
65 bus_space_tag_t sc_bst;
66 bus_space_handle_t sc_bsh;
67 bus_size_t sc_bsz;
68 struct sdhc_host *sc_host;
69 void *sc_ih;
70
71 struct fdtbus_gpio_pin *sc_pin_cd;
72 struct fdtbus_gpio_pin *sc_pin_power;
73 struct fdtbus_gpio_pin *sc_pin_wp;
74
75 struct fdtbus_regulator *sc_reg_vqmmc;
76 };
77
78 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc),
79 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL);
80
81 static const struct device_compatible_entry compat_data[] = {
82 { .compat = "nvidia,tegra210-sdhci" },
83 { .compat = "nvidia,tegra124-sdhci" },
84 DEVICE_COMPAT_EOL
85 };
86
87 static int
tegra_sdhc_match(device_t parent,cfdata_t cf,void * aux)88 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux)
89 {
90 struct fdt_attach_args * const faa = aux;
91
92 return of_compatible_match(faa->faa_phandle, compat_data);
93 }
94
95 static void
tegra_sdhc_attach(device_t parent,device_t self,void * aux)96 tegra_sdhc_attach(device_t parent, device_t self, void *aux)
97 {
98 struct tegra_sdhc_softc * const sc = device_private(self);
99 struct fdt_attach_args * const faa = aux;
100 char intrstr[128];
101 bus_addr_t addr;
102 bus_size_t size;
103 u_int bus_width;
104 int error;
105
106 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
107 aprint_error(": couldn't get registers\n");
108 return;
109 }
110
111 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width))
112 bus_width = 4;
113
114 sc->sc.sc_dev = self;
115 sc->sc.sc_dmat = faa->faa_dmat;
116
117 #ifdef _LP64
118 error = bus_dmatag_subregion(faa->faa_dmat, 0, __MASK(32),
119 &sc->sc.sc_dmat, BUS_DMA_WAITOK);
120 if (error != 0) {
121 aprint_error(": couldn't create DMA tag: %d\n", error);
122 return;
123 }
124 #endif
125
126 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS |
127 SDHC_FLAG_NO_PWR0 |
128 SDHC_FLAG_NO_CLKBASE |
129 SDHC_FLAG_NO_TIMEOUT |
130 SDHC_FLAG_SINGLE_POWER_WRITE |
131 SDHC_FLAG_NO_HS_BIT |
132 SDHC_FLAG_USE_DMA |
133 SDHC_FLAG_BROKEN_ADMA2_ZEROLEN;
134 if (bus_width == 8) {
135 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
136 }
137 sc->sc.sc_host = &sc->sc_host;
138
139 sc->sc_bst = faa->faa_bst;
140 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
141 if (error) {
142 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
143 return;
144 }
145 sc->sc_bsz = size;
146
147 #ifdef TEGRA_SDHC_NO_SDR104
148 /* XXX SDR104 requires a custom tuning method on Tegra K1 */
149 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
150 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
151 SDHC_CAPABILITIES);
152 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
153 SDHC_CAPABILITIES2);
154 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP;
155 #endif
156
157 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle,
158 "power-gpios", GPIO_PIN_OUTPUT);
159 if (sc->sc_pin_power)
160 fdtbus_gpio_write(sc->sc_pin_power, 1);
161
162 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle,
163 "cd-gpios", GPIO_PIN_INPUT);
164 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle,
165 "wp-gpios", GPIO_PIN_INPUT);
166
167 if (sc->sc_pin_cd) {
168 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect;
169 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET;
170 }
171 if (sc->sc_pin_wp) {
172 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect;
173 }
174
175 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle,
176 "vqmmc-supply");
177 if (sc->sc_reg_vqmmc) {
178 sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage;
179 } else {
180 /* Regulator required for UHS signaling */
181 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
182 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
183 SDHC_CAPABILITIES);
184 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
185 SDHC_CAPABILITIES2);
186 sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP);
187 }
188
189 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
190 if (sc->sc_clk == NULL) {
191 aprint_error(": couldn't get clock\n");
192 return;
193 }
194 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci");
195 if (sc->sc_rst == NULL) {
196 aprint_error(": couldn't get reset\n");
197 return;
198 }
199
200 fdtbus_reset_assert(sc->sc_rst);
201 #ifdef TEGRA_SDHC_NO_SDR104
202 error = clk_set_rate(sc->sc_clk, 100000000);
203 #else
204 error = clk_set_rate(sc->sc_clk, 204000000);
205 #endif
206 if (error) {
207 aprint_error(": couldn't set frequency: %d\n", error);
208 return;
209 }
210 error = clk_enable(sc->sc_clk);
211 if (error) {
212 aprint_error(": couldn't enable clock: %d\n", error);
213 return;
214 }
215 fdtbus_reset_deassert(sc->sc_rst);
216
217 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
218
219 aprint_naive("\n");
220 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase);
221
222 if (sc->sc.sc_clkbase == 0) {
223 aprint_error_dev(self, "couldn't determine frequency\n");
224 return;
225 }
226
227 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
228 aprint_error_dev(self, "failed to decode interrupt\n");
229 return;
230 }
231
232 sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_SDMMC,
233 0, sdhc_intr, &sc->sc, device_xname(self));
234 if (sc->sc_ih == NULL) {
235 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
236 intrstr);
237 return;
238 }
239 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
240
241 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
242 if (error) {
243 aprint_error_dev(self, "couldn't initialize host, error = %d\n",
244 error);
245 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih);
246 sc->sc_ih = NULL;
247 return;
248 }
249 }
250
251 static int
tegra_sdhc_card_detect(struct sdhc_softc * ssc)252 tegra_sdhc_card_detect(struct sdhc_softc *ssc)
253 {
254 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
255
256 KASSERT(sc->sc_pin_cd != NULL);
257
258 return fdtbus_gpio_read(sc->sc_pin_cd);
259 }
260
261 static int
tegra_sdhc_write_protect(struct sdhc_softc * ssc)262 tegra_sdhc_write_protect(struct sdhc_softc *ssc)
263 {
264 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
265
266 KASSERT(sc->sc_pin_wp != NULL);
267
268 return fdtbus_gpio_read(sc->sc_pin_wp);
269 }
270
271 static int
tegra_sdhc_signal_voltage(struct sdhc_softc * ssc,int signal_voltage)272 tegra_sdhc_signal_voltage(struct sdhc_softc *ssc, int signal_voltage)
273 {
274 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
275 u_int uvol;
276 int error;
277
278 KASSERT(sc->sc_reg_vqmmc != NULL);
279
280 switch (signal_voltage) {
281 case SDMMC_SIGNAL_VOLTAGE_330:
282 uvol = 3300000;
283 break;
284 case SDMMC_SIGNAL_VOLTAGE_180:
285 uvol = 1800000;
286 break;
287 default:
288 return EINVAL;
289 }
290
291 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol);
292 if (error != 0)
293 return error;
294
295 return fdtbus_regulator_enable(sc->sc_reg_vqmmc);
296 }
297