xref: /netbsd-src/sys/arch/arm/nvidia/tegra_rtc.c (revision 946379e7b37692fc43f68eb0d1c10daa0a7f3b6c)
1 /* $NetBSD: tegra_rtc.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_rtc.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/kmem.h>
39 
40 #include <dev/clock_subr.h>
41 
42 #include <arm/nvidia/tegra_reg.h>
43 #include <arm/nvidia/tegra_rtcreg.h>
44 #include <arm/nvidia/tegra_var.h>
45 
46 #include <dev/fdt/fdtvar.h>
47 
48 static int	tegra_rtc_match(device_t, cfdata_t, void *);
49 static void	tegra_rtc_attach(device_t, device_t, void *);
50 
51 struct tegra_rtc_softc {
52 	device_t		sc_dev;
53 	bus_space_tag_t		sc_bst;
54 	bus_space_handle_t	sc_bsh;
55 
56 	struct todr_chip_handle	sc_todr;
57 };
58 
59 static int	tegra_rtc_gettime(todr_chip_handle_t, struct timeval *);
60 static int	tegra_rtc_settime(todr_chip_handle_t, struct timeval *);
61 
62 CFATTACH_DECL_NEW(tegra_rtc, sizeof(struct tegra_rtc_softc),
63 	tegra_rtc_match, tegra_rtc_attach, NULL, NULL);
64 
65 #define RTC_READ(sc, reg)	\
66 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
67 #define RTC_WRITE(sc, reg, val)	\
68 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
69 
70 static int
71 tegra_rtc_match(device_t parent, cfdata_t cf, void *aux)
72 {
73 	const char * const compatible[] = { "nvidia,tegra124-rtc", NULL };
74 	struct fdt_attach_args * const faa = aux;
75 
76 	return of_match_compatible(faa->faa_phandle, compatible);
77 }
78 
79 static void
80 tegra_rtc_attach(device_t parent, device_t self, void *aux)
81 {
82 	struct tegra_rtc_softc * const sc = device_private(self);
83 	struct fdt_attach_args * const faa = aux;
84 	bus_addr_t addr;
85 	bus_size_t size;
86 	int error;
87 
88 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
89 		aprint_error(": couldn't get registers\n");
90 		return;
91 	}
92 
93 	sc->sc_dev = self;
94 	sc->sc_bst = faa->faa_bst;
95 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
96 	if (error) {
97 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
98 		return;
99 	}
100 
101 	aprint_naive("\n");
102 	aprint_normal(": RTC\n");
103 
104 	sc->sc_todr.todr_gettime = tegra_rtc_gettime;
105 	sc->sc_todr.todr_settime = tegra_rtc_settime;
106 	sc->sc_todr.cookie = sc;
107 	todr_attach(&sc->sc_todr);
108 }
109 
110 static int
111 tegra_rtc_gettime(todr_chip_handle_t tch, struct timeval *tv)
112 {
113 	struct tegra_rtc_softc * const sc = tch->cookie;
114 
115 	tv->tv_sec = RTC_READ(sc, RTC_SECONDS_REG);
116 	tv->tv_usec = 0;
117 
118 	return 0;
119 }
120 
121 static int
122 tegra_rtc_settime(todr_chip_handle_t tch, struct timeval *tv)
123 {
124 	struct tegra_rtc_softc * const sc = tch->cookie;
125 	int retry = 500;
126 
127 	while (--retry > 0) {
128 		if ((RTC_READ(sc, RTC_BUSY_REG) & RTC_BUSY_STATUS) == 0)
129 			break;
130 		delay(1);
131 	}
132 	if (retry == 0) {
133 		device_printf(sc->sc_dev, "RTC write failed (BUSY)\n");
134 		return ETIMEDOUT;
135 	}
136 
137 	RTC_WRITE(sc, RTC_SECONDS_REG, tv->tv_sec);
138 
139 	return 0;
140 }
141