1 /* $NetBSD: tegra_rtc.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_rtc.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/kmem.h>
39
40 #include <dev/clock_subr.h>
41
42 #include <arm/nvidia/tegra_reg.h>
43 #include <arm/nvidia/tegra_rtcreg.h>
44 #include <arm/nvidia/tegra_var.h>
45
46 #include <dev/fdt/fdtvar.h>
47
48 static int tegra_rtc_match(device_t, cfdata_t, void *);
49 static void tegra_rtc_attach(device_t, device_t, void *);
50
51 struct tegra_rtc_softc {
52 device_t sc_dev;
53 bus_space_tag_t sc_bst;
54 bus_space_handle_t sc_bsh;
55
56 struct todr_chip_handle sc_todr;
57 };
58
59 static int tegra_rtc_gettime(todr_chip_handle_t, struct timeval *);
60 static int tegra_rtc_settime(todr_chip_handle_t, struct timeval *);
61
62 CFATTACH_DECL_NEW(tegra_rtc, sizeof(struct tegra_rtc_softc),
63 tegra_rtc_match, tegra_rtc_attach, NULL, NULL);
64
65 #define RTC_READ(sc, reg) \
66 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
67 #define RTC_WRITE(sc, reg, val) \
68 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
69
70 static const struct device_compatible_entry compat_data[] = {
71 { .compat = "nvidia,tegra210-rtc" },
72 { .compat = "nvidia,tegra124-rtc" },
73 { .compat = "nvidia,tegra20-rtc" },
74 DEVICE_COMPAT_EOL
75 };
76
77 static int
tegra_rtc_match(device_t parent,cfdata_t cf,void * aux)78 tegra_rtc_match(device_t parent, cfdata_t cf, void *aux)
79 {
80 struct fdt_attach_args * const faa = aux;
81
82 return of_compatible_match(faa->faa_phandle, compat_data);
83 }
84
85 static void
tegra_rtc_attach(device_t parent,device_t self,void * aux)86 tegra_rtc_attach(device_t parent, device_t self, void *aux)
87 {
88 struct tegra_rtc_softc * const sc = device_private(self);
89 struct fdt_attach_args * const faa = aux;
90 bus_addr_t addr;
91 bus_size_t size;
92 int error;
93
94 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
95 aprint_error(": couldn't get registers\n");
96 return;
97 }
98
99 sc->sc_dev = self;
100 sc->sc_bst = faa->faa_bst;
101 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
102 if (error) {
103 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
104 return;
105 }
106
107 aprint_naive("\n");
108 aprint_normal(": RTC\n");
109
110 sc->sc_todr.todr_gettime = tegra_rtc_gettime;
111 sc->sc_todr.todr_settime = tegra_rtc_settime;
112 sc->sc_todr.cookie = sc;
113 fdtbus_todr_attach(self, faa->faa_phandle, &sc->sc_todr);
114 }
115
116 static int
tegra_rtc_gettime(todr_chip_handle_t tch,struct timeval * tv)117 tegra_rtc_gettime(todr_chip_handle_t tch, struct timeval *tv)
118 {
119 struct tegra_rtc_softc * const sc = tch->cookie;
120
121 tv->tv_sec = RTC_READ(sc, RTC_SECONDS_REG);
122 tv->tv_usec = 0;
123
124 return 0;
125 }
126
127 static int
tegra_rtc_settime(todr_chip_handle_t tch,struct timeval * tv)128 tegra_rtc_settime(todr_chip_handle_t tch, struct timeval *tv)
129 {
130 struct tegra_rtc_softc * const sc = tch->cookie;
131 int retry = 500;
132
133 while (--retry > 0) {
134 if ((RTC_READ(sc, RTC_BUSY_REG) & RTC_BUSY_STATUS) == 0)
135 break;
136 delay(1);
137 }
138 if (retry == 0) {
139 device_printf(sc->sc_dev, "RTC write failed (BUSY)\n");
140 return ETIMEDOUT;
141 }
142
143 RTC_WRITE(sc, RTC_SECONDS_REG, tv->tv_sec);
144
145 return 0;
146 }
147