1 /* $NetBSD: tegra_pmc.c,v 1.16 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.16 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38
39 #include <arm/nvidia/tegra_reg.h>
40 #include <arm/nvidia/tegra_pmcreg.h>
41 #include <arm/nvidia/tegra_var.h>
42
43 #include <dev/fdt/fdtvar.h>
44
45 static int tegra_pmc_match(device_t, cfdata_t, void *);
46 static void tegra_pmc_attach(device_t, device_t, void *);
47
48 struct tegra_pmc_softc {
49 device_t sc_dev;
50 bus_space_tag_t sc_bst;
51 bus_space_handle_t sc_bsh;
52 };
53
54 static struct tegra_pmc_softc *pmc_softc = NULL;
55
56 CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc),
57 tegra_pmc_match, tegra_pmc_attach, NULL, NULL);
58
59 static const struct device_compatible_entry compat_data[] = {
60 { .compat = "nvidia,tegra210-pmc" },
61 { .compat = "nvidia,tegra124-pmc" },
62 DEVICE_COMPAT_EOL
63 };
64
65 static int
tegra_pmc_match(device_t parent,cfdata_t cf,void * aux)66 tegra_pmc_match(device_t parent, cfdata_t cf, void *aux)
67 {
68 struct fdt_attach_args * const faa = aux;
69
70 return of_compatible_match(faa->faa_phandle, compat_data);
71 }
72
73 static void
tegra_pmc_attach(device_t parent,device_t self,void * aux)74 tegra_pmc_attach(device_t parent, device_t self, void *aux)
75 {
76 struct tegra_pmc_softc * const sc = device_private(self);
77 struct fdt_attach_args * const faa = aux;
78 bus_addr_t addr;
79 bus_size_t size;
80 int error;
81
82 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
83 aprint_error(": couldn't get registers\n");
84 return;
85 }
86
87 sc->sc_dev = self;
88 sc->sc_bst = faa->faa_bst;
89 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
90 if (error) {
91 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
92 return;
93 }
94
95 KASSERT(pmc_softc == NULL);
96 pmc_softc = sc;
97
98 aprint_naive("\n");
99 aprint_normal(": PMC\n");
100 }
101
102 static void
tegra_pmc_get_bs(bus_space_tag_t * pbst,bus_space_handle_t * pbsh)103 tegra_pmc_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
104 {
105 if (pmc_softc) {
106 *pbst = pmc_softc->sc_bst;
107 *pbsh = pmc_softc->sc_bsh;
108 } else {
109 extern struct bus_space arm_generic_bs_tag;
110
111 *pbst = &arm_generic_bs_tag;
112
113 bus_space_subregion(*pbst, tegra_apb_bsh,
114 TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, pbsh);
115 }
116 }
117
118 void
tegra_pmc_reset(void)119 tegra_pmc_reset(void)
120 {
121 bus_space_tag_t bst;
122 bus_space_handle_t bsh;
123 uint32_t cntrl;
124
125 tegra_pmc_get_bs(&bst, &bsh);
126
127 cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG);
128 cntrl |= PMC_CNTRL_0_MAIN_RST;
129 bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl);
130
131 for (;;) {
132 __asm("wfi");
133 }
134 }
135
136 void
tegra_pmc_power(u_int partid,bool enable)137 tegra_pmc_power(u_int partid, bool enable)
138 {
139 bus_space_tag_t bst;
140 bus_space_handle_t bsh;
141 uint32_t status, toggle;
142 bool state;
143 int retry = 10000;
144
145 tegra_pmc_get_bs(&bst, &bsh);
146
147 status = bus_space_read_4(bst, bsh, PMC_PWRGATE_STATUS_0_REG);
148 state = !!(status & __BIT(partid));
149 if (state == enable)
150 return;
151
152 while (--retry > 0) {
153 toggle = bus_space_read_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG);
154 if ((toggle & PMC_PWRGATE_TOGGLE_0_START) == 0)
155 break;
156 delay(1);
157 }
158 if (retry == 0) {
159 printf("ERROR: Couldn't enable PMC partition %#x\n", partid);
160 return;
161 }
162
163 bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG,
164 __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |
165 PMC_PWRGATE_TOGGLE_0_START);
166 }
167
168 void
tegra_pmc_remove_clamping(u_int partid)169 tegra_pmc_remove_clamping(u_int partid)
170 {
171 bus_space_tag_t bst;
172 bus_space_handle_t bsh;
173
174 tegra_pmc_get_bs(&bst, &bsh);
175
176 if (partid == PMC_PARTID_TD) {
177 /*
178 * On Tegra124 and later, the GPU power clamping is
179 * controlled by a separate register
180 */
181 bus_space_write_4(bst, bsh, PMC_GPU_RG_CNTRL_REG, 0);
182 return;
183 }
184
185 bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG,
186 __BIT(partid));
187 }
188
189 void
tegra_pmc_hdmi_enable(void)190 tegra_pmc_hdmi_enable(void)
191 {
192 bus_space_tag_t bst;
193 bus_space_handle_t bsh;
194
195 tegra_pmc_get_bs(&bst, &bsh);
196
197 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG,
198 0, PMC_IO_DPD_STATUS_HDMI);
199 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD2_STATUS_REG,
200 0, PMC_IO_DPD2_STATUS_HV);
201 }
202