xref: /netbsd-src/sys/arch/arm/nvidia/tegra_pinmux.h (revision 36e99b00d0ed949aa7fca2d10aad044231ae226a)
1 /* $NetBSD: tegra_pinmux.h,v 1.2 2019/09/28 07:42:47 skrll Exp $ */
2 
3 /*-
4  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef _ARM_TEGRA_PINMUX_H
30 #define	_ARM_TEGRA_PINMUX_H
31 
32 #include "opt_tegra.h"
33 
34 #define TEGRA_PINMUX_MAXFUNC	4
35 
36 struct tegra_pinmux_pins {
37 	const char *tpp_name;
38 	u_int tpp_reg;
39 	enum tegra_pin_type {
40 		TEGRA_PINMUX,
41 		TEGRA_PADCTRL
42 	} tpp_type;
43 	union {
44 		const char *tpp_functions[TEGRA_PINMUX_MAXFUNC];
45 		struct {
46 			uint32_t	drvdn_mask;
47 			uint32_t	drvup_mask;
48 			uint32_t	slwrr_mask;
49 			uint32_t	slwrf_mask;
50 		} tpp_dg;
51 	};
52 };
53 
54 struct tegra_pinmux_conf {
55 	uint32_t npins;
56 	const struct tegra_pinmux_pins *pins;
57 };
58 
59 #ifdef SOC_TEGRA210
60 extern const struct tegra_pinmux_conf tegra210_pinmux_conf;
61 #endif
62 
63 #endif /* _ARM_TEGRA_PINMUX_H */
64