1 /* $NetBSD: tegra_intr.h,v 1.12 2017/05/30 22:00:25 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_INTR_H 30 #define _ARM_TEGRA_INTR_H 31 32 #define TEGRA_INTR(x) ((x) + 32) 33 34 #define TEGRA_INTR_TMR1 TEGRA_INTR(0) 35 #define TEGRA_INTR_TMR2 TEGRA_INTR(1) 36 #define TEGRA_INTR_CEC TEGRA_INTR(3) 37 #define TEGRA_INTR_SDMMC1 TEGRA_INTR(14) 38 #define TEGRA_INTR_SDMMC2 TEGRA_INTR(15) 39 #define TEGRA_INTR_SDMMC3 TEGRA_INTR(19) 40 #define TEGRA_INTR_USB1 TEGRA_INTR(20) 41 #define TEGRA_INTR_USB2 TEGRA_INTR(21) 42 #define TEGRA_INTR_SATA TEGRA_INTR(23) 43 #define TEGRA_INTR_SDMMC4 TEGRA_INTR(31) 44 #define TEGRA_INTR_UARTA TEGRA_INTR(36) 45 #define TEGRA_INTR_UARTB TEGRA_INTR(37) 46 #define TEGRA_INTR_I2C1 TEGRA_INTR(38) 47 #define TEGRA_INTR_TMR3 TEGRA_INTR(41) 48 #define TEGRA_INTR_TMR4 TEGRA_INTR(42) 49 #define TEGRA_INTR_UARTC TEGRA_INTR(46) 50 #define TEGRA_INTR_THERMAL TEGRA_INTR(48) 51 #define TEGRA_INTR_I2C5 TEGRA_INTR(53) 52 #define TEGRA_INTR_I2C6 TEGRA_INTR(63) 53 #define TEGRA_INTR_HOST1X_SYNCPT_COP TEGRA_INTR(64) 54 #define TEGRA_INTR_HOST1X_SYNCPT_CPU TEGRA_INTR(65) 55 #define TEGRA_INTR_HOST1X_GEN_COP TEGRA_INTR(66) 56 #define TEGRA_INTR_HOST1X_GEN_CPU TEGRA_INTR(67) 57 #define TEGRA_INTR_MSENC TEGRA_INTR(68) 58 #define TEGRA_INTR_VI TEGRA_INTR(69) 59 #define TEGRA_INTR_ISPB TEGRA_INTR(70) 60 #define TEGRA_INTR_ISP TEGRA_INTR(71) 61 #define TEGRA_INTR_VIC TEGRA_INTR(72) 62 #define TEGRA_INTR_DISPLAYA TEGRA_INTR(73) 63 #define TEGRA_INTR_DISPLAYB TEGRA_INTR(74) 64 #define TEGRA_INTR_HDMI TEGRA_INTR(75) 65 #define TEGRA_INTR_SOR TEGRA_INTR(76) 66 #define TEGRA_INTR_MC TEGRA_INTR(77) 67 #define TEGRA_INTR_EMC TEGRA_INTR(78) 68 #define TEGRA_INTR_SPI6 TEGRA_INTR(79) 69 #define TEGRA_INTR_HDA TEGRA_INTR(81) 70 #define TEGRA_INTR_SPI2 TEGRA_INTR(82) 71 #define TEGRA_INTR_SPI3 TEGRA_INTR(83) 72 #define TEGRA_INTR_I2C2 TEGRA_INTR(84) 73 #define TEGRA_INTR_PMU_EXT TEGRA_INTR(86) 74 #define TEGRA_INTR_GPIO6 TEGRA_INTR(87) 75 #define TEGRA_INTR_GPIO7 TEGRA_INTR(89) 76 #define TEGRA_INTR_UARTD TEGRA_INTR(90) 77 #define TEGRA_INTR_I2C3 TEGRA_INTR(92) 78 #define TEGRA_INTR_SW_INTR TEGRA_INTR(95) 79 #define TEGRA_INTR_SNOR TEGRA_INTR(96) 80 #define TEGRA_INTR_USB3 TEGRA_INTR(97) 81 #define TEGRA_INTR_PCIE_INT TEGRA_INTR(98) 82 #define TEGRA_INTR_PCIE_MSI TEGRA_INTR(99) 83 #define TEGRA_INTR_PCIE_WAKE TEGRA_INTR(100) 84 #define TEGRA_INTR_I2C4 TEGRA_INTR(120) 85 #define TEGRA_INTR_TMR5 TEGRA_INTR(121) 86 #define TEGRA_INTR_WDT_CPU TEGRA_INTR(123) 87 #define TEGRA_INTR_WDT_AVP TEGRA_INTR(124) 88 #define TEGRA_INTR_TMR6 TEGRA_INTR(152) 89 #define TEGRA_INTR_TMR7 TEGRA_INTR(153) 90 #define TEGRA_INTR_TMR8 TEGRA_INTR(154) 91 #define TEGRA_INTR_TMR9 TEGRA_INTR(155) 92 #define TEGRA_INTR_TMR0 TEGRA_INTR(156) 93 #define TEGRA_INTR_GPU TEGRA_INTR(157) 94 #define TEGRA_INTR_GPU_NONSTALL TEGRA_INTR(158) 95 96 #endif /* _ARM_TEGRA_INTR_H */ 97