1 /* $NetBSD: tegra_i2creg.h,v 1.2 2015/05/16 21:31:39 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_I2CREG_H 30 #define _ARM_TEGRA_I2CREG_H 31 32 #define I2C_CNFG_REG 0x00 33 #define I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT __BIT(15) 34 #define I2C_CNFG_DEBOUNCE_CNT __BITS(14,12) 35 #define I2C_CNFG_NEW_MASTER_FSM __BIT(11) 36 #define I2C_CNFG_PACKET_MODE_EN __BIT(10) 37 #define I2C_CNFG_SEND __BIT(9) 38 #define I2C_CNFG_NOACK __BIT(8) 39 #define I2C_CNFG_CMD2 __BIT(7) 40 #define I2C_CNFG_CMD1 __BIT(6) 41 #define I2C_CNFG_START __BIT(5) 42 #define I2C_CNFG_SLV2 __BIT(4) 43 #define I2C_CNFG_LENGTH __BITS(3,1) 44 #define I2C_CNFG_A_MOD __BIT(0) 45 46 #define I2C_CMD_ADDR0_REG 0x04 47 #define I2C_CMD_ADDR1_REG 0x08 48 #define I2C_CMD_DATA1_REG 0x0c 49 #define I2C_CMD_DATA2_REG 0x10 50 51 #define I2C_STATUS_REG 0x1c 52 #define I2C_STATUS_BUSY __BIT(8) 53 #define I2C_STATUS_CMD2_STAT __BITS(7,4) 54 #define I2C_STATUS_CMD1_STAT __BITS(3,0) 55 56 #define I2C_SL_CNFG_REG 0x20 57 #define I2C_SL_CNFG_FIFO_XFER_EN __BIT(20) 58 #define I2C_SL_CNFG_BUFFER_SIZE __BITS(19,8) 59 #define I2C_SL_CNFG_ACK_LAST_BYTE_VALID __BIT(7) 60 #define I2C_SL_CNFG_ACK_LAST_BYTE __BIT(6) 61 #define I2C_SL_CNFG_ACK_WITHHOLD_EN __BIT(5) 62 #define I2C_SL_CNFG_PKT_MODE_EN __BIT(4) 63 #define I2C_SL_CNFG_ENABLE_SL __BIT(3) 64 #define I2C_SL_CNFG_NEWSL __BIT(2) 65 #define I2C_SL_CNFG_NACK __BIT(1) 66 #define I2C_SL_CNFG_RESP __BIT(0) 67 68 #define I2C_SL_RCVD_REG 0x24 69 #define I2C_SL_STATUS_REG 0x28 70 #define I2C_SL_ADDR1_REG 0x2c 71 #define I2C_SL_ADDR2_REG 0x30 72 #define I2C_TLOW_SEXT_REG 0x34 73 #define I2C_SL_DELAY_COUNT_REG 0x3c 74 #define I2C_SL_INT_MASK_REG 0x40 75 #define I2C_SL_INT_SOURCE_REG 0x44 76 #define I2C_SL_INT_SET_REG 0x48 77 #define I2C_TX_PACKET_FIFO_REG 0x50 78 #define I2C_RX_FIFO_REG 0x54 79 80 #define I2C_PACKET_TRANSFER_STATUS_REG 0x58 81 #define I2C_PACKET_TRANSFER_STATUS_TRANSFER_COMPLETE __BIT(24) 82 #define I2C_PACKET_TRANSFER_STATUS_TRANSFER_PKT_ID __BITS(23,16) 83 #define I2C_PACKET_TRANSFER_STATUS_TRANSFER_BYTENUM __BITS(15,4) 84 #define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR __BIT(3) 85 #define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_DATA __BIT(2) 86 #define I2C_PACKET_TRANSFER_STATUS_ARB_LOST __BIT(1) 87 #define I2C_PACKET_TRANSFER_STATUS_CONTROLLER_BUSY __BIT(0) 88 89 #define I2C_FIFO_CONTROL_REG 0x5c 90 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG __BITS(15,13) 91 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG __BITS(12,10) 92 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH __BIT(9) 93 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH __BIT(8) 94 #define I2C_FIFO_CONTROL_TX_FIFO_TRIG __BITS(7,5) 95 #define I2C_FIFO_CONTROL_RX_FIFO_TRIG __BITS(4,2) 96 #define I2C_FIFO_CONTROL_TX_FIFO_FLUSH __BIT(1) 97 #define I2C_FIFO_CONTROL_RX_FIFO_FLUSH __BIT(0) 98 99 #define I2C_FIFO_STATUS_REG 0x60 100 #define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON __BIT(25) 101 #define I2C_FIFO_STATUS_SLV_TX_FIFO_EMPTY_CNT __BITS(23,20) 102 #define I2C_FIFO_STATUS_SLV_RX_FIFO_FULL_CNT __BITS(19,16) 103 #define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT __BITS(7,4) 104 #define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT __BITS(3,0) 105 106 #define I2C_INTERRUPT_MASK_REG 0x64 107 #define I2C_INTERRUPT_MASK_TIMEOUT __BIT(8) 108 #define I2C_INTERRUPT_MASK_PACKET_XFER_COMPLETE __BIT(7) 109 #define I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE __BIT(6) 110 #define I2C_INTERRUPT_MASK_NOACK __BIT(3) 111 #define I2C_INTERRUPT_MASK_ARB_LOST __BIT(2) 112 #define I2C_INTERRUPT_MASK_TFIFO_DATA_REQ __BIT(1) 113 #define I2C_INTERRUPT_MASK_RFIFO_DATA_REQ __BIT(0) 114 115 #define I2C_INTERRUPT_STATUS_REG 0x68 116 #define I2C_INTERRUPT_STATUS_TIMEOUT __BIT(8) 117 #define I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE __BIT(7) 118 #define I2C_INTERRUPT_STATUS_ALL_PACKETS_XFER_COMPLETE __BIT(6) 119 #define I2C_INTERRUPT_STATUS_NOACK __BIT(3) 120 #define I2C_INTERRUPT_STATUS_ARB_LOST __BIT(2) 121 #define I2C_INTERRUPT_STATUS_TFIFO_DATA_REQ __BIT(1) 122 #define I2C_INTERRUPT_STATUS_RFIFO_DATA_REQ __BIT(0) 123 124 #define I2C_CLK_DIVISOR_REG 0x6c 125 #define I2C_CLK_DIVISOR_STD_FAST_MODE __BITS(31,16) 126 #define I2C_CLK_DIVISOR_HSMODE __BITS(15,0) 127 128 #define I2C_INTERRUPT_SOURCE_REG 0x70 129 #define I2C_INTERRUPT_SET_REG 0x74 130 #define I2C_SLV_TX_PACKET_FIFO_REG 0x78 131 #define I2C_SLV_RX_FIFO_REG 0x7c 132 #define I2C_SLV_PACKET_STATUS_REG 0x80 133 #define I2C_BUS_CLEAR_CONFIG_REG 0x84 134 #define I2C_BUS_CLEAR_STATUS_REG 0x88 135 136 #define I2C_BUS_CONFIG_LOAD_REG 0x8c 137 #define I2C_BUS_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD __BIT(2) 138 #define I2C_BUS_CONFIG_LOAD_SLV_CONFIG_LOAD __BIT(1) 139 #define I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD __BIT(0) 140 141 #define I2C_INTERFACE_TIMING0_REG 0x94 142 #define I2C_INTERFACE_TIMING0_THIGH __BITS(13,8) 143 #define I2C_INTERFACE_TIMING0_TLOW __BITS(5,0) 144 145 #define I2C_INTERFACE_TIMING1_REG 0x98 146 #define I2C_HS_INTERFACE_TIMING0_REG 0x9c 147 #define I2C_HS_INTERFACE_TIMING1_REG 0xa0 148 149 /* 150 * I/O Packets 151 */ 152 #define I2C_IOPACKET_WORD0_PROTHDRSZ __BITS(29,28) 153 #define I2C_IOPACKET_WORD0_PROTHDRSZ_REQ 0 154 #define I2C_IOPACKET_WORD0_PROTHDRSZ_RES 1 155 #define I2C_IOPACKET_WORD0_PKTID __BITS(23,16) 156 #define I2C_IOPACKET_WORD0_CONTROLLERID __BITS(15,12) 157 #define I2C_IOPACKET_WORD0_PROTOCOL __BITS(7,4) 158 #define I2C_IOPACKET_WORD0_PROTOCOL_I2C 1 159 #define I2C_IOPACKET_WORD0_PKTTYPE __BITS(2,0) 160 #define I2C_IOPACKET_WORD0_PKTTYPE_REQ 0 161 #define I2C_IOPACKET_WORD0_PKTTYPE_RES 1 162 #define I2C_IOPACKET_WORD0_PKTTYPE_INT 2 163 #define I2C_IOPACKET_WORD0_PKTTYPE_STOP 3 164 165 #define I2C_IOPACKET_WORD1_PAYLOADSIZE __BITS(11,0) 166 167 #define I2C_IOPACKET_XMITHDR_RESP_PKT_FREQ __BIT(25) 168 #define I2C_IOPACKET_XMITHDR_RESP_PKT_ENABLE __BIT(24) 169 #define I2C_IOPACKET_XMITHDR_HS_MODE __BIT(22) 170 #define I2C_IOPACKET_XMITHDR_CONTINUE_ON_NACK __BIT(21) 171 #define I2C_IOPACKET_XMITHDR_SEND_START_BYTE __BIT(20) 172 #define I2C_IOPACKET_XMITHDR_READ __BIT(19) 173 #define I2C_IOPACKET_XMITHDR_ADDRESS_MODE __BIT(18) 174 #define I2C_IOPACKET_XMITHDR_IE __BIT(17) 175 #define I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP __BIT(16) 176 #define I2C_IOPACKET_XMITHDR_CONTINUE_XFER __BIT(15) 177 #define I2C_IOPACKET_XMITHDR_HS_MASTER_ADDR __BITS(14,12) 178 #define I2C_IOPACKET_XMITHDR_SLAVE_ADDR __BITS(9,0) 179 180 #define I2C_IOPACKET_RESPHDR_RFIFO_OVF __BIT(26) 181 #define I2C_IOPACKET_RESPHDR_TFIFO_OVF __BIT(25) 182 #define I2C_IOPACKET_RESPHDR_TRANSFER_COMPLETE __BIT(24) 183 #define I2C_IOPACKET_RESPHDR_TRANSFER_PKT_ID __BITS(23,16) 184 #define I2C_IOPACKET_RESPHDR_TRANSFER_BYTENUM __BITS(15,4) 185 #define I2C_IOPACKET_RESPHDR_NOACK_FOR_ADDR __BIT(3) 186 #define I2C_IOPACKET_RESPHDR_NOACK_FOR_DATA __BIT(2) 187 #define I2C_IOPACKET_RESPHDR_ARB_LOST __BIT(1) 188 #define I2C_IOPACKET_RESPHDR_CONTROLLER_BUSY __BIT(0) 189 190 #endif /* _ARM_TEGRA_I2CREG_H */ 191