1 /* $NetBSD: tegra_fuse.c,v 1.9 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_fuse.c,v 1.9 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38
39 #include <arm/nvidia/tegra_reg.h>
40 #include <arm/nvidia/tegra_var.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 static int tegra_fuse_match(device_t, cfdata_t, void *);
45 static void tegra_fuse_attach(device_t, device_t, void *);
46
47 struct tegra_fuse_softc {
48 device_t sc_dev;
49 bus_space_tag_t sc_bst;
50 bus_space_handle_t sc_bsh;
51
52 struct clk *sc_clk;
53 struct fdtbus_reset *sc_rst;
54 };
55
56 static struct tegra_fuse_softc *fuse_softc = NULL;
57
58 CFATTACH_DECL_NEW(tegra_fuse, sizeof(struct tegra_fuse_softc),
59 tegra_fuse_match, tegra_fuse_attach, NULL, NULL);
60
61 static const struct device_compatible_entry compat_data[] = {
62 { .compat = "nvidia,tegra210-efuse" },
63 { .compat = "nvidia,tegra124-efuse" },
64 DEVICE_COMPAT_EOL
65 };
66
67 static int
tegra_fuse_match(device_t parent,cfdata_t cf,void * aux)68 tegra_fuse_match(device_t parent, cfdata_t cf, void *aux)
69 {
70 struct fdt_attach_args * const faa = aux;
71
72 return of_compatible_match(faa->faa_phandle, compat_data);
73 }
74
75 static void
tegra_fuse_attach(device_t parent,device_t self,void * aux)76 tegra_fuse_attach(device_t parent, device_t self, void *aux)
77 {
78 struct tegra_fuse_softc * const sc = device_private(self);
79 struct fdt_attach_args * const faa = aux;
80 bus_addr_t addr;
81 bus_size_t size;
82 int error;
83
84 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
85 aprint_error(": couldn't get registers\n");
86 return;
87 }
88 sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "fuse");
89 if (sc->sc_clk == NULL) {
90 aprint_error(": couldn't get clock fuse\n");
91 return;
92 }
93 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "fuse");
94 if (sc->sc_rst == NULL) {
95 aprint_error(": couldn't get reset fuse\n");
96 return;
97 }
98
99 sc->sc_dev = self;
100 sc->sc_bst = faa->faa_bst;
101 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
102 if (error) {
103 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
104 return;
105 }
106
107 KASSERT(fuse_softc == NULL);
108 fuse_softc = sc;
109
110 aprint_naive("\n");
111 aprint_normal(": FUSE\n");
112 }
113
114 uint32_t
tegra_fuse_read(u_int offset)115 tegra_fuse_read(u_int offset)
116 {
117 bus_space_tag_t bst;
118 bus_space_handle_t bsh;
119
120 KASSERT(fuse_softc != NULL);
121
122 bst = fuse_softc->sc_bst;
123 bsh = fuse_softc->sc_bsh;
124
125 clk_enable(fuse_softc->sc_clk);
126 const uint32_t v = bus_space_read_4(bst, bsh, 0x100 + offset);
127 clk_disable(fuse_softc->sc_clk);
128
129 return v;
130 }
131