1 /* $NetBSD: tegra_drm_mode.c,v 1.12 2015/12/23 11:58:10 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.12 2015/12/23 11:58:10 jmcneill Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <dev/i2c/ddcvar.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_intr.h> 42 #include <arm/nvidia/tegra_pmcreg.h> 43 #include <arm/nvidia/tegra_dcreg.h> 44 #include <arm/nvidia/tegra_hdmireg.h> 45 #include <arm/nvidia/tegra_drm.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 static struct drm_framebuffer *tegra_fb_create(struct drm_device *, 50 struct drm_file *, struct drm_mode_fb_cmd2 *); 51 52 static const struct drm_mode_config_funcs tegra_mode_config_funcs = { 53 .fb_create = tegra_fb_create 54 }; 55 56 static int tegra_framebuffer_create_handle(struct drm_framebuffer *, 57 struct drm_file *, unsigned int *); 58 static void tegra_framebuffer_destroy(struct drm_framebuffer *); 59 60 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = { 61 .create_handle = tegra_framebuffer_create_handle, 62 .destroy = tegra_framebuffer_destroy 63 }; 64 65 static int tegra_crtc_init(struct drm_device *, int); 66 static void tegra_crtc_destroy(struct drm_crtc *); 67 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *, 68 uint32_t, uint32_t, uint32_t); 69 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int); 70 static int tegra_crtc_intr(void *); 71 72 static const struct drm_crtc_funcs tegra_crtc_funcs = { 73 .cursor_set = tegra_crtc_cursor_set, 74 .cursor_move = tegra_crtc_cursor_move, 75 .set_config = drm_crtc_helper_set_config, 76 .destroy = tegra_crtc_destroy 77 }; 78 79 static void tegra_crtc_dpms(struct drm_crtc *, int); 80 static bool tegra_crtc_mode_fixup(struct drm_crtc *, 81 const struct drm_display_mode *, 82 struct drm_display_mode *); 83 static int tegra_crtc_mode_set(struct drm_crtc *, 84 struct drm_display_mode *, struct drm_display_mode *, 85 int, int, struct drm_framebuffer *); 86 static int tegra_crtc_mode_set_base(struct drm_crtc *, 87 int, int, struct drm_framebuffer *); 88 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *, 89 struct drm_framebuffer *, int, int, enum mode_set_atomic); 90 static void tegra_crtc_disable(struct drm_crtc *); 91 static void tegra_crtc_prepare(struct drm_crtc *); 92 static void tegra_crtc_commit(struct drm_crtc *); 93 94 static int tegra_crtc_do_set_base(struct drm_crtc *, 95 struct drm_framebuffer *, int, int, int); 96 97 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 98 .dpms = tegra_crtc_dpms, 99 .mode_fixup = tegra_crtc_mode_fixup, 100 .mode_set = tegra_crtc_mode_set, 101 .mode_set_base = tegra_crtc_mode_set_base, 102 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic, 103 .disable = tegra_crtc_disable, 104 .prepare = tegra_crtc_prepare, 105 .commit = tegra_crtc_commit 106 }; 107 108 static int tegra_encoder_init(struct drm_device *); 109 static void tegra_encoder_destroy(struct drm_encoder *); 110 111 static const struct drm_encoder_funcs tegra_encoder_funcs = { 112 .destroy = tegra_encoder_destroy 113 }; 114 115 static void tegra_encoder_dpms(struct drm_encoder *, int); 116 static bool tegra_encoder_mode_fixup(struct drm_encoder *, 117 const struct drm_display_mode *, struct drm_display_mode *); 118 static void tegra_encoder_mode_set(struct drm_encoder *, 119 struct drm_display_mode *, struct drm_display_mode *); 120 static void tegra_encoder_prepare(struct drm_encoder *); 121 static void tegra_encoder_commit(struct drm_encoder *); 122 123 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = { 124 .dpms = tegra_encoder_dpms, 125 .mode_fixup = tegra_encoder_mode_fixup, 126 .prepare = tegra_encoder_prepare, 127 .commit = tegra_encoder_commit, 128 .mode_set = tegra_encoder_mode_set 129 }; 130 131 static int tegra_connector_init(struct drm_device *, struct drm_encoder *); 132 static void tegra_connector_destroy(struct drm_connector *); 133 static enum drm_connector_status tegra_connector_detect(struct drm_connector *, 134 bool); 135 136 static const struct drm_connector_funcs tegra_connector_funcs = { 137 .dpms = drm_helper_connector_dpms, 138 .detect = tegra_connector_detect, 139 .fill_modes = drm_helper_probe_single_connector_modes, 140 .destroy = tegra_connector_destroy 141 }; 142 143 static int tegra_connector_mode_valid(struct drm_connector *, 144 struct drm_display_mode *); 145 static int tegra_connector_get_modes(struct drm_connector *); 146 static struct drm_encoder *tegra_connector_best_encoder(struct drm_connector *); 147 148 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = { 149 .mode_valid = tegra_connector_mode_valid, 150 .get_modes = tegra_connector_get_modes, 151 .best_encoder = tegra_connector_best_encoder 152 }; 153 154 static const struct tegra_hdmi_tmds_config { 155 u_int dot_clock; 156 uint32_t sor_pll0; 157 uint32_t sor_pll1; 158 uint32_t sor_lane_drive_current; 159 uint32_t pe_current; 160 uint32_t sor_io_peak_current; 161 uint32_t sor_pad_ctls0; 162 uint32_t car_plld_misc; /* XXX unused? */ 163 } tegra_hdmi_tmds_config[] = { 164 /* 480p */ 165 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 166 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 167 /* 720p / 1080i */ 168 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 169 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 170 /* 1080p */ 171 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 172 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 173 /* 2160p */ 174 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 175 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 176 }; 177 178 int 179 tegra_drm_mode_init(struct drm_device *ddev) 180 { 181 int error; 182 183 drm_mode_config_init(ddev); 184 ddev->mode_config.min_width = 0; 185 ddev->mode_config.min_height = 0; 186 ddev->mode_config.max_width = 4096; 187 ddev->mode_config.max_height = 2160; 188 ddev->mode_config.funcs = &tegra_mode_config_funcs; 189 190 error = tegra_crtc_init(ddev, 0); 191 if (error) 192 return error; 193 194 error = tegra_crtc_init(ddev, 1); 195 if (error) 196 return error; 197 198 error = tegra_encoder_init(ddev); 199 if (error) 200 return error; 201 202 error = drm_vblank_init(ddev, 2); 203 if (error) 204 return error; 205 206 return 0; 207 } 208 209 int 210 tegra_drm_framebuffer_init(struct drm_device *ddev, 211 struct tegra_framebuffer *fb) 212 { 213 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs); 214 } 215 216 static struct drm_framebuffer * 217 tegra_fb_create(struct drm_device *ddev, struct drm_file *file, 218 struct drm_mode_fb_cmd2 *cmd) 219 { 220 struct tegra_framebuffer *fb; 221 struct drm_gem_object *gem_obj; 222 int error; 223 224 if (cmd->flags) 225 return NULL; 226 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 && 227 cmd->pixel_format != DRM_FORMAT_XRGB8888) { 228 return NULL; 229 } 230 231 gem_obj = drm_gem_object_lookup(ddev, file, cmd->handles[0]); 232 if (gem_obj == NULL) 233 return NULL; 234 235 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP); 236 if (fb == NULL) 237 goto unref; 238 239 fb->obj = to_tegra_gem_obj(gem_obj); 240 fb->base.pitches[0] = cmd->pitches[0]; 241 fb->base.offsets[0] = cmd->offsets[0]; 242 fb->base.width = cmd->width; 243 fb->base.height = cmd->height; 244 fb->base.pixel_format = cmd->pixel_format; 245 drm_fb_get_bpp_depth(cmd->pixel_format, &fb->base.depth, 246 &fb->base.bits_per_pixel); 247 248 error = tegra_drm_framebuffer_init(ddev, fb); 249 if (error) 250 goto dealloc; 251 252 return &fb->base; 253 254 drm_framebuffer_cleanup(&fb->base); 255 dealloc: 256 kmem_free(fb, sizeof(*fb)); 257 unref: 258 drm_gem_object_unreference_unlocked(gem_obj); 259 260 return NULL; 261 } 262 263 static int 264 tegra_framebuffer_create_handle(struct drm_framebuffer *fb, 265 struct drm_file *file, unsigned int *handle) 266 { 267 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 268 269 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle); 270 } 271 272 static void 273 tegra_framebuffer_destroy(struct drm_framebuffer *fb) 274 { 275 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 276 277 drm_framebuffer_cleanup(fb); 278 drm_gem_object_unreference_unlocked(&tegra_fb->obj->base); 279 kmem_free(tegra_fb, sizeof(*tegra_fb)); 280 } 281 282 static int 283 tegra_crtc_init(struct drm_device *ddev, int index) 284 { 285 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 286 struct tegra_crtc *crtc; 287 struct clk *clk_parent; 288 bus_addr_t offset; 289 bus_size_t size; 290 u_int intr; 291 int error; 292 293 if (sc->sc_clk_dc[index] == NULL || 294 sc->sc_clk_dc_parent[index] == NULL || 295 sc->sc_rst_dc[index] == NULL) { 296 DRM_ERROR("no clocks configured for crtc %d\n", index); 297 return -EIO; 298 } 299 300 switch (index) { 301 case 0: 302 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET; 303 size = TEGRA_DISPLAYA_SIZE; 304 intr = TEGRA_INTR_DISPLAYA; 305 break; 306 case 1: 307 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET; 308 size = TEGRA_DISPLAYB_SIZE; 309 intr = TEGRA_INTR_DISPLAYB; 310 break; 311 default: 312 return -EINVAL; 313 } 314 315 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP); 316 if (crtc == NULL) 317 return -ENOMEM; 318 319 crtc->index = index; 320 crtc->bst = sc->sc_bst; 321 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh); 322 if (error) { 323 kmem_free(crtc, sizeof(*crtc)); 324 return -error; 325 } 326 crtc->size = size; 327 crtc->intr = intr; 328 crtc->ih = intr_establish(intr, IPL_VM, IST_LEVEL | IST_MPSAFE, 329 tegra_crtc_intr, crtc); 330 if (crtc->ih == NULL) { 331 DRM_ERROR("failed to establish interrupt for crtc %d\n", index); 332 } 333 const size_t cursor_size = 256 * 256 * 4; 334 crtc->cursor_obj = tegra_drm_obj_alloc(ddev, cursor_size); 335 if (crtc->cursor_obj == NULL) { 336 kmem_free(crtc, sizeof(*crtc)); 337 return -ENOMEM; 338 } 339 340 /* Enter reset */ 341 fdtbus_reset_assert(sc->sc_rst_dc[index]); 342 343 /* Turn on power to display partition */ 344 const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB; 345 tegra_pmc_power(pmc_partid, true); 346 tegra_pmc_remove_clamping(pmc_partid); 347 348 /* Set parent clock */ 349 clk_parent = clk_get("pll_d2_out0"); 350 if (clk_parent == NULL) { 351 DRM_ERROR("couldn't find pll_d2_out0\n"); 352 return -EIO; 353 } 354 error = clk_set_parent(sc->sc_clk_dc[index], clk_parent); 355 if (error) { 356 DRM_ERROR("failed to set crtc %d clock parent: %d\n", 357 index, error); 358 return -error; 359 } 360 361 /* Enable DC clock */ 362 error = clk_enable(sc->sc_clk_dc[index]); 363 if (error) { 364 DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error); 365 return -error; 366 } 367 368 /* Leave reset */ 369 fdtbus_reset_deassert(sc->sc_rst_dc[index]); 370 371 crtc->clk_parent = clk_parent; 372 373 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK); 374 375 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs); 376 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs); 377 378 return 0; 379 } 380 381 static int 382 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 383 uint32_t handle, uint32_t width, uint32_t height) 384 { 385 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 386 struct drm_gem_object *gem_obj = NULL; 387 struct tegra_gem_object *obj; 388 uint32_t cfg, opt; 389 int error; 390 391 if (tegra_crtc->enabled == false) 392 return 0; 393 394 if (handle == 0) { 395 /* hide cursor */ 396 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 397 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) { 398 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 399 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 400 /* Commit settings */ 401 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 402 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 403 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 404 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 405 } 406 error = 0; 407 goto done; 408 } 409 410 if ((width != height) || 411 (width != 32 && width != 64 && width != 128 && width != 256)) { 412 DRM_ERROR("Cursor dimension %ux%u not supported\n", 413 width, height); 414 error = -EINVAL; 415 goto done; 416 } 417 418 gem_obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 419 if (gem_obj == NULL) { 420 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n", 421 handle, tegra_crtc->index); 422 error = -ENOENT; 423 goto done; 424 } 425 obj = to_tegra_gem_obj(gem_obj); 426 427 if (obj->base.size < width * height * 4) { 428 DRM_ERROR("Cursor buffer is too small\n"); 429 error = -ENOMEM; 430 goto done; 431 } 432 433 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY, 434 DC_DISP_CURSOR_START_ADDR_CLIPPING); 435 switch (width) { 436 case 32: 437 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32, 438 DC_DISP_CURSOR_START_ADDR_SIZE); 439 break; 440 case 64: 441 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64, 442 DC_DISP_CURSOR_START_ADDR_SIZE); 443 break; 444 case 128: 445 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128, 446 DC_DISP_CURSOR_START_ADDR_SIZE); 447 break; 448 case 256: 449 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256, 450 DC_DISP_CURSOR_START_ADDR_SIZE); 451 break; 452 } 453 454 /* copy cursor (argb -> rgba) */ 455 struct tegra_gem_object *cursor_obj = tegra_crtc->cursor_obj; 456 uint32_t off, *cp = obj->dmap, *crtc_cp = cursor_obj->dmap; 457 for (off = 0; off < width * height; off++) { 458 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24); 459 } 460 461 const uint64_t paddr = cursor_obj->dmasegs[0].ds_addr; 462 463 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG, 464 (paddr >> 32) & 3); 465 cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff, 466 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO); 467 const uint32_t ocfg = 468 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG); 469 if (cfg != ocfg) { 470 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg); 471 } 472 473 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG); 474 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL; 475 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL); 476 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL; 477 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL); 478 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA; 479 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA); 480 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL; 481 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg); 482 483 /* set cursor position */ 484 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 485 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) | 486 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V)); 487 488 /* Commit settings */ 489 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 490 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 491 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 492 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 493 494 /* show cursor */ 495 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 496 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) { 497 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 498 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 499 500 /* Commit settings */ 501 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 502 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 503 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 504 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 505 } 506 507 error = 0; 508 509 done: 510 if (error == 0) { 511 /* Wait for activation request to complete */ 512 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) & 513 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ) 514 ; 515 } 516 517 if (gem_obj) { 518 drm_gem_object_unreference_unlocked(gem_obj); 519 } 520 521 return error; 522 } 523 524 static int 525 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 526 { 527 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 528 529 tegra_crtc->cursor_x = x & 0x3fff; 530 tegra_crtc->cursor_y = y & 0x3fff; 531 532 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 533 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) | 534 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V)); 535 536 /* Commit settings */ 537 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 538 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 539 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 540 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 541 542 return 0; 543 } 544 545 static void 546 tegra_crtc_destroy(struct drm_crtc *crtc) 547 { 548 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 549 drm_crtc_cleanup(crtc); 550 if (tegra_crtc->ih) { 551 intr_disestablish(tegra_crtc->ih); 552 } 553 tegra_drm_obj_free(tegra_crtc->cursor_obj); 554 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size); 555 kmem_free(tegra_crtc, sizeof(*tegra_crtc)); 556 } 557 558 static void 559 tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 560 { 561 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 562 563 switch (mode) { 564 case DRM_MODE_DPMS_ON: 565 case DRM_MODE_DPMS_STANDBY: 566 case DRM_MODE_DPMS_SUSPEND: 567 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 568 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0); 569 break; 570 case DRM_MODE_DPMS_OFF: 571 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 572 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 573 break; 574 } 575 } 576 577 static bool 578 tegra_crtc_mode_fixup(struct drm_crtc *crtc, 579 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 580 { 581 return true; 582 } 583 584 static int 585 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 586 struct drm_display_mode *adjusted_mode, int x, int y, 587 struct drm_framebuffer *old_fb) 588 { 589 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 590 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 591 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end; 592 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; 593 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 594 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 595 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay; 596 597 /* Set colour depth to ARGB8888 */ 598 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG, 599 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8, 600 DC_WINC_A_COLOR_DEPTH_DEPTH)); 601 602 /* Disable byte swapping */ 603 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG, 604 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP, 605 DC_WINC_A_BYTE_SWAP_SWAP)); 606 607 /* Initial DDA */ 608 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0); 609 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0); 610 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000); 611 612 /* Window position, size, stride */ 613 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG, 614 __SHIFTIN(0, DC_WINC_A_POSITION_V) | 615 __SHIFTIN(0, DC_WINC_A_POSITION_H)); 616 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG, 617 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) | 618 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H)); 619 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG, 620 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) | 621 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 622 DC_WINC_A_PRESCALED_SIZE_H)); 623 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG, 624 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 625 DC_WINC_A_LINE_STRIDE_LINE_STRIDE)); 626 627 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 628 629 /* Enable window A */ 630 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 631 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 632 633 /* Timing and signal options */ 634 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG, 635 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS)); 636 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG, 637 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888, 638 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE)); 639 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG, 640 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE); 641 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG, 642 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE, 643 DC_DISP_H_PULSE2_CONTROL_V_QUAL) | 644 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A, 645 DC_DISP_H_PULSE2_CONTROL_LAST)); 646 647 const u_int pulse_start = 1 + hspw + hbp - 10; 648 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG, 649 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) | 650 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END)); 651 652 /* Pixel clock */ 653 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); 654 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2; 655 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG, 656 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) | 657 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER)); 658 659 /* Mode timings */ 660 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG, 661 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) | 662 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H)); 663 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG, 664 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) | 665 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H)); 666 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG, 667 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) | 668 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H)); 669 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG, 670 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) | 671 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H)); 672 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG, 673 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) | 674 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H)); 675 676 return 0; 677 } 678 679 static int 680 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 681 int x, int y, int atomic) 682 { 683 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 684 struct tegra_framebuffer *tegra_fb = atomic ? 685 to_tegra_framebuffer(fb) : 686 to_tegra_framebuffer(crtc->primary->fb); 687 688 uint64_t paddr = (uint64_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr; 689 690 /* Framebuffer start address */ 691 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3); 692 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff); 693 694 /* Offsets */ 695 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x); 696 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y); 697 698 /* Surface kind */ 699 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG, 700 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH, 701 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND)); 702 703 return 0; 704 } 705 706 static int 707 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 708 struct drm_framebuffer *old_fb) 709 { 710 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 711 712 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 713 714 /* Commit settings */ 715 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 716 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 717 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 718 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 719 720 return 0; 721 } 722 723 static int 724 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 725 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) 726 { 727 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 728 729 tegra_crtc_do_set_base(crtc, fb, x, y, 1); 730 731 /* Commit settings */ 732 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 733 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 734 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 735 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 736 737 return 0; 738 } 739 740 static void 741 tegra_crtc_disable(struct drm_crtc *crtc) 742 { 743 } 744 745 static void 746 tegra_crtc_prepare(struct drm_crtc *crtc) 747 { 748 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 749 750 /* Access control */ 751 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0); 752 753 /* Enable window A programming */ 754 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG, 755 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT); 756 } 757 758 static void 759 tegra_crtc_commit(struct drm_crtc *crtc) 760 { 761 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 762 763 /* Enable continuous display mode */ 764 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG, 765 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY, 766 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE)); 767 768 /* Enable power */ 769 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG, 770 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE | 771 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE | 772 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE | 773 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE | 774 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE | 775 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE | 776 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE, 777 0); 778 779 /* Commit settings */ 780 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 781 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 782 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 783 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 784 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 785 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 786 787 tegra_crtc->enabled = true; 788 } 789 790 static int 791 tegra_encoder_init(struct drm_device *ddev) 792 { 793 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 794 struct tegra_encoder *encoder; 795 int error; 796 797 if (sc->sc_clk_hdmi == NULL || 798 sc->sc_clk_hdmi_parent == NULL || 799 sc->sc_rst_hdmi == NULL) { 800 DRM_ERROR("no clocks configured for hdmi\n"); 801 DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 802 DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi); 803 return -EIO; 804 } 805 806 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP); 807 if (encoder == NULL) 808 return -ENOMEM; 809 810 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET; 811 const bus_size_t size = TEGRA_HDMI_SIZE; 812 813 encoder->bst = sc->sc_bst; 814 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh); 815 if (error) { 816 kmem_free(encoder, sizeof(*encoder)); 817 return -error; 818 } 819 encoder->size = size; 820 821 tegra_pmc_hdmi_enable(); 822 823 /* Enable parent PLL */ 824 error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000); 825 if (error) { 826 DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error); 827 return -error; 828 } 829 error = clk_enable(sc->sc_clk_hdmi_parent); 830 if (error) { 831 DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error); 832 return -error; 833 } 834 835 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs, 836 DRM_MODE_ENCODER_TMDS); 837 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs); 838 839 encoder->base.possible_crtcs = (1 << 0) | (1 << 1); 840 841 return tegra_connector_init(ddev, &encoder->base); 842 } 843 844 static void 845 tegra_encoder_destroy(struct drm_encoder *encoder) 846 { 847 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 848 drm_encoder_cleanup(encoder); 849 kmem_free(tegra_encoder, sizeof(*tegra_encoder)); 850 } 851 852 static void 853 tegra_encoder_dpms(struct drm_encoder *encoder, int mode) 854 { 855 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 856 857 if (encoder->crtc == NULL) 858 return; 859 860 switch (mode) { 861 case DRM_MODE_DPMS_ON: 862 case DRM_MODE_DPMS_STANDBY: 863 case DRM_MODE_DPMS_SUSPEND: 864 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 865 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE); 866 break; 867 case DRM_MODE_DPMS_OFF: 868 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 869 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0); 870 break; 871 } 872 } 873 874 static bool 875 tegra_encoder_mode_fixup(struct drm_encoder *encoder, 876 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 877 { 878 return true; 879 } 880 881 static int 882 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate) 883 { 884 struct drm_device *ddev = encoder->dev; 885 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 886 int error; 887 888 /* Enter reset */ 889 fdtbus_reset_assert(sc->sc_rst_hdmi); 890 891 /* Set HDMI parent clock */ 892 error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 893 if (error) { 894 DRM_ERROR("couldn't set hdmi parent: %d\n", error); 895 return -error; 896 } 897 898 /* Set dot clock frequency */ 899 error = clk_set_rate(sc->sc_clk_hdmi, rate); 900 if (error) { 901 DRM_ERROR("couldn't set hdmi clock: %d\n", error); 902 return -error; 903 } 904 error = clk_enable(sc->sc_clk_hdmi); 905 if (error) { 906 DRM_ERROR("couldn't enable hdmi clock: %d\n", error); 907 return -error; 908 } 909 910 /* Leave reset */ 911 fdtbus_reset_deassert(sc->sc_rst_hdmi); 912 913 return 0; 914 } 915 916 static void 917 tegra_encoder_mode_set(struct drm_encoder *encoder, 918 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 919 { 920 struct drm_device *ddev = encoder->dev; 921 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 922 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc); 923 struct tegra_connector *tegra_connector = NULL; 924 struct drm_connector *connector; 925 const struct tegra_hdmi_tmds_config *tmds = NULL; 926 uint32_t input_ctrl; 927 int retry; 928 u_int i; 929 930 tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000); 931 932 /* find the connector for this encoder */ 933 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 934 if (connector->encoder == encoder) { 935 tegra_connector = to_tegra_connector(connector); 936 break; 937 } 938 } 939 940 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) { 941 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) { 942 break; 943 } 944 } 945 if (i < __arraycount(tegra_hdmi_tmds_config)) { 946 tmds = &tegra_hdmi_tmds_config[i]; 947 } else { 948 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 949 } 950 951 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 952 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 953 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 954 tmds->sor_lane_drive_current); 955 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG, 956 tmds->pe_current); 957 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 958 tmds->sor_io_peak_current); 959 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 960 tmds->sor_pad_ctls0); 961 962 const u_int div = (mode->crtc_clock / 1000) * 4; 963 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG, 964 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 965 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 966 967 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG, 968 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 969 HDMI_NV_PDISP_SOR_CSTM_MODE) | 970 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 971 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 972 HDMI_NV_PDISP_SOR_CSTM_MODE | 973 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 974 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 975 976 const uint32_t inst = 977 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 978 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 979 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 980 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 981 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 982 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 983 984 input_ctrl = __SHIFTIN(tegra_crtc->index, 985 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 986 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480) 987 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 988 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 989 990 /* Start SOR */ 991 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 992 0, 993 HDMI_NV_PDISP_SOR_PLL0_PWR | 994 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 995 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 996 delay(10); 997 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 998 0, 999 HDMI_NV_PDISP_SOR_PLL0_PDBG); 1000 1001 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 1002 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 1003 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 1004 1005 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 1006 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 1007 1008 for (retry = 10000; retry > 0; retry--) { 1009 const uint32_t pwr = HDMI_READ(tegra_encoder, 1010 HDMI_NV_PDISP_SOR_PWR_REG); 1011 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 1012 break; 1013 delay(10); 1014 } 1015 if (retry == 0) { 1016 DRM_ERROR("timeout enabling SOR power\n"); 1017 } 1018 1019 uint32_t state2 = 1020 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 1021 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 1022 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 1023 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 1024 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1025 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 1026 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1027 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 1028 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 1029 1030 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1031 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 1032 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 1033 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 1034 1035 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1036 1037 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 1038 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 1039 1040 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1041 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 1042 1043 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1044 1045 const u_int rekey = 56; 1046 const u_int hspw = mode->hsync_end - mode->hsync_start; 1047 const u_int hbp = mode->htotal - mode->hsync_end; 1048 const u_int hfp = mode->hsync_start - mode->hdisplay; 1049 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 1050 uint32_t ctrl = 1051 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 1052 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 1053 if (tegra_connector && tegra_connector->has_hdmi_sink) { 1054 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 1055 } 1056 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 1057 1058 if (tegra_connector && tegra_connector->has_hdmi_sink && 1059 tegra_connector->has_audio) { 1060 struct hdmi_audio_infoframe ai; 1061 struct hdmi_avi_infoframe avii; 1062 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1063 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1064 const u_int n = 6144; /* 48 kHz */ 1065 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480; 1066 1067 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG, 1068 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO, 1069 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) | 1070 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL); 1071 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 1072 HDMI_NV_PDISP_AUDIO_N_RESETF | 1073 HDMI_NV_PDISP_AUDIO_N_GENERATE | 1074 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE)); 1075 1076 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG, 1077 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS | 1078 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS | 1079 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL)); 1080 1081 /* 1082 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by 1083 * software in the 44.1 kHz register regardless of chosen rate. 1084 */ 1085 HDMI_WRITE(tegra_encoder, 1086 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG, 1087 cts << 8); 1088 HDMI_WRITE(tegra_encoder, 1089 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG, 1090 0x80000000 | n); 1091 1092 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0, 1093 HDMI_NV_PDISP_AUDIO_N_RESETF); 1094 1095 HDMI_WRITE(tegra_encoder, 1096 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000); 1097 1098 hdmi_audio_infoframe_init(&ai); 1099 ai.channels = 2; 1100 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf)); 1101 HDMI_WRITE(tegra_encoder, 1102 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG, 1103 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16)); 1104 HDMI_WRITE(tegra_encoder, 1105 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG, 1106 aibuf[3] | (aibuf[4] << 8) | 1107 (aibuf[5] << 16) | (aibuf[6] << 24)); 1108 HDMI_WRITE(tegra_encoder, 1109 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG, 1110 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16)); 1111 1112 hdmi_avi_infoframe_init(&avii); 1113 drm_hdmi_avi_infoframe_from_display_mode(&avii, mode); 1114 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf)); 1115 HDMI_WRITE(tegra_encoder, 1116 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG, 1117 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16)); 1118 HDMI_WRITE(tegra_encoder, 1119 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG, 1120 aviibuf[3] | (aviibuf[4] << 8) | 1121 (aviibuf[5] << 16) | (aviibuf[6] << 24)); 1122 HDMI_WRITE(tegra_encoder, 1123 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG, 1124 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16)); 1125 HDMI_WRITE(tegra_encoder, 1126 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG, 1127 aviibuf[10] | (aviibuf[11] << 8) | 1128 (aviibuf[12] << 16) | (aviibuf[13] << 24)); 1129 HDMI_WRITE(tegra_encoder, 1130 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG, 1131 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16)); 1132 1133 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 1134 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO); 1135 HDMI_WRITE(tegra_encoder, 1136 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 1137 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE); 1138 HDMI_WRITE(tegra_encoder, 1139 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 1140 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE); 1141 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1142 } else { 1143 HDMI_WRITE(tegra_encoder, 1144 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 1145 HDMI_WRITE(tegra_encoder, 1146 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 1147 HDMI_WRITE(tegra_encoder, 1148 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 1149 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1150 } 1151 1152 /* Enable DC output to HDMI */ 1153 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, 1154 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0); 1155 1156 /* Commit settings */ 1157 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1158 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 1159 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 1160 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1161 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 1162 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 1163 } 1164 1165 static void 1166 tegra_encoder_prepare(struct drm_encoder *encoder) 1167 { 1168 } 1169 1170 static void 1171 tegra_encoder_commit(struct drm_encoder *encoder) 1172 { 1173 } 1174 1175 static int 1176 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder) 1177 { 1178 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1179 struct tegra_connector *connector; 1180 1181 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP); 1182 if (connector == NULL) 1183 return -ENOMEM; 1184 1185 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs, 1186 DRM_MODE_CONNECTOR_HDMIA); 1187 drm_connector_helper_add(&connector->base, 1188 &tegra_connector_helper_funcs); 1189 1190 connector->base.interlace_allowed = 0; 1191 connector->base.doublescan_allowed = 0; 1192 1193 drm_sysfs_connector_add(&connector->base); 1194 1195 connector->base.polled = 1196 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1197 1198 drm_mode_connector_attach_encoder(&connector->base, encoder); 1199 1200 connector->hpd = sc->sc_pin_hpd; 1201 if (!connector->hpd) 1202 DRM_ERROR("failed to find hpd pin for connector\n"); 1203 1204 connector->ddc = sc->sc_ddc; 1205 if (!connector->ddc) 1206 DRM_ERROR("failed to find ddc device for connector\n"); 1207 1208 return 0; 1209 } 1210 1211 static void 1212 tegra_connector_destroy(struct drm_connector *connector) 1213 { 1214 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1215 1216 drm_sysfs_connector_remove(connector); 1217 drm_connector_cleanup(connector); 1218 kmem_free(tegra_connector, sizeof(*tegra_connector)); 1219 } 1220 1221 static enum drm_connector_status 1222 tegra_connector_detect(struct drm_connector *connector, bool force) 1223 { 1224 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1225 bool con; 1226 1227 1228 if (!tegra_connector->hpd) { 1229 tegra_connector->has_hdmi_sink = false; 1230 tegra_connector->has_audio = false; 1231 return connector_status_connected; 1232 } 1233 1234 con = fdtbus_gpio_read(tegra_connector->hpd); 1235 if (con) { 1236 return connector_status_connected; 1237 } else { 1238 prop_dictionary_t prop = device_properties(connector->dev->dev); 1239 prop_dictionary_remove(prop, "physical-address"); 1240 tegra_connector->has_hdmi_sink = false; 1241 tegra_connector->has_audio = false; 1242 return connector_status_disconnected; 1243 } 1244 } 1245 1246 static int 1247 tegra_connector_mode_valid(struct drm_connector *connector, 1248 struct drm_display_mode *mode) 1249 { 1250 return MODE_OK; 1251 } 1252 1253 static int 1254 tegra_connector_get_modes(struct drm_connector *connector) 1255 { 1256 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1257 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev); 1258 prop_dictionary_t prop = device_properties(connector->dev->dev); 1259 char edid[EDID_LENGTH * 4]; 1260 struct edid *pedid = NULL; 1261 int error, block; 1262 1263 if (tegra_connector->ddc) { 1264 memset(edid, 0, sizeof(edid)); 1265 for (block = 0; block < 4; block++) { 1266 error = ddc_read_edid_block(tegra_connector->ddc, 1267 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 1268 if (error) 1269 break; 1270 if (block == 0) { 1271 pedid = (struct edid *)edid; 1272 if (edid[0x7e] == 0) 1273 break; 1274 } 1275 } 1276 } 1277 1278 if (pedid) { 1279 if (sc->sc_force_dvi) { 1280 tegra_connector->has_hdmi_sink = false; 1281 tegra_connector->has_audio = false; 1282 } else { 1283 tegra_connector->has_hdmi_sink = 1284 drm_detect_hdmi_monitor(pedid); 1285 tegra_connector->has_audio = 1286 drm_detect_monitor_audio(pedid); 1287 } 1288 drm_mode_connector_update_edid_property(connector, pedid); 1289 error = drm_add_edid_modes(connector, pedid); 1290 drm_edid_to_eld(connector, pedid); 1291 if (drm_detect_hdmi_monitor(pedid)) { 1292 prop_dictionary_set_uint16(prop, "physical-address", 1293 connector->physical_address); 1294 } 1295 return error; 1296 } else { 1297 drm_mode_connector_update_edid_property(connector, NULL); 1298 return 0; 1299 } 1300 } 1301 1302 static struct drm_encoder * 1303 tegra_connector_best_encoder(struct drm_connector *connector) 1304 { 1305 int enc_id = connector->encoder_ids[0]; 1306 struct drm_mode_object *obj; 1307 struct drm_encoder *encoder = NULL; 1308 1309 if (enc_id) { 1310 obj = drm_mode_object_find(connector->dev, enc_id, 1311 DRM_MODE_OBJECT_ENCODER); 1312 if (obj == NULL) 1313 return NULL; 1314 encoder = obj_to_encoder(obj); 1315 } 1316 1317 return encoder; 1318 } 1319 1320 static int 1321 tegra_crtc_intr(void *priv) 1322 { 1323 struct tegra_crtc *tegra_crtc = priv; 1324 struct drm_device *ddev = tegra_crtc->base.dev; 1325 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1326 int rv = 0; 1327 1328 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG); 1329 1330 if (status & DC_CMD_INT_V_BLANK) { 1331 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1332 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]); 1333 drm_handle_vblank(ddev, tegra_crtc->index); 1334 rv = 1; 1335 } 1336 1337 return rv; 1338 } 1339 1340 u32 1341 tegra_drm_get_vblank_counter(struct drm_device *ddev, int crtc) 1342 { 1343 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1344 1345 if (crtc > 1) 1346 return 0; 1347 1348 return sc->sc_vbl_received[crtc]; 1349 } 1350 1351 int 1352 tegra_drm_enable_vblank(struct drm_device *ddev, int crtc) 1353 { 1354 struct tegra_crtc *tegra_crtc = NULL; 1355 struct drm_crtc *iter; 1356 1357 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1358 if (to_tegra_crtc(iter)->index == crtc) { 1359 tegra_crtc = to_tegra_crtc(iter); 1360 break; 1361 } 1362 } 1363 if (tegra_crtc == NULL) 1364 return -EINVAL; 1365 1366 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0); 1367 1368 return 0; 1369 } 1370 1371 void 1372 tegra_drm_disable_vblank(struct drm_device *ddev, int crtc) 1373 { 1374 struct tegra_crtc *tegra_crtc = NULL; 1375 struct drm_crtc *iter; 1376 1377 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1378 if (to_tegra_crtc(iter)->index == crtc) { 1379 tegra_crtc = to_tegra_crtc(iter); 1380 break; 1381 } 1382 } 1383 if (tegra_crtc == NULL) 1384 return; 1385 1386 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK); 1387 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1388 } 1389