1 /* $NetBSD: tegra_drm_mode.c,v 1.21 2021/12/19 12:44:14 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.21 2021/12/19 12:44:14 riastradh Exp $");
31
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_drv.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_plane_helper.h>
37 #include <drm/drm_probe_helper.h>
38 #include <drm/drm_vblank.h>
39
40 #include <dev/i2c/ddcvar.h>
41
42 #include <arm/nvidia/tegra_reg.h>
43 #include <arm/nvidia/tegra_var.h>
44 #include <arm/nvidia/tegra_intr.h>
45 #include <arm/nvidia/tegra_pmcreg.h>
46 #include <arm/nvidia/tegra_dcreg.h>
47 #include <arm/nvidia/tegra_hdmireg.h>
48 #include <arm/nvidia/tegra_drm.h>
49
50 #include <dev/fdt/fdtvar.h>
51
52 #include <external/bsd/drm2/dist/drm/drm_internal.h>
53
54 static struct drm_framebuffer *tegra_fb_create(struct drm_device *,
55 struct drm_file *, const struct drm_mode_fb_cmd2 *);
56
57 static const struct drm_mode_config_funcs tegra_mode_config_funcs = {
58 .fb_create = tegra_fb_create
59 };
60
61 static int tegra_framebuffer_create_handle(struct drm_framebuffer *,
62 struct drm_file *, unsigned int *);
63 static void tegra_framebuffer_destroy(struct drm_framebuffer *);
64
65 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = {
66 .create_handle = tegra_framebuffer_create_handle,
67 .destroy = tegra_framebuffer_destroy
68 };
69
70 static int tegra_crtc_init(struct drm_device *, int);
71 static void tegra_crtc_destroy(struct drm_crtc *);
72 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *,
73 uint32_t, uint32_t, uint32_t);
74 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int);
75 static int tegra_crtc_intr(void *);
76
77 static const struct drm_crtc_funcs tegra_crtc_funcs = {
78 .cursor_set = tegra_crtc_cursor_set,
79 .cursor_move = tegra_crtc_cursor_move,
80 .set_config = drm_crtc_helper_set_config,
81 .destroy = tegra_crtc_destroy
82 };
83
84 static void tegra_crtc_dpms(struct drm_crtc *, int);
85 static bool tegra_crtc_mode_fixup(struct drm_crtc *,
86 const struct drm_display_mode *,
87 struct drm_display_mode *);
88 static int tegra_crtc_mode_set(struct drm_crtc *,
89 struct drm_display_mode *, struct drm_display_mode *,
90 int, int, struct drm_framebuffer *);
91 static int tegra_crtc_mode_set_base(struct drm_crtc *,
92 int, int, struct drm_framebuffer *);
93 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *,
94 struct drm_framebuffer *, int, int, enum mode_set_atomic);
95 static void tegra_crtc_disable(struct drm_crtc *);
96 static void tegra_crtc_prepare(struct drm_crtc *);
97 static void tegra_crtc_commit(struct drm_crtc *);
98
99 static int tegra_crtc_do_set_base(struct drm_crtc *,
100 struct drm_framebuffer *, int, int, int);
101
102 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
103 .dpms = tegra_crtc_dpms,
104 .mode_fixup = tegra_crtc_mode_fixup,
105 .mode_set = tegra_crtc_mode_set,
106 .mode_set_base = tegra_crtc_mode_set_base,
107 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic,
108 .disable = tegra_crtc_disable,
109 .prepare = tegra_crtc_prepare,
110 .commit = tegra_crtc_commit
111 };
112
113 static int tegra_encoder_init(struct drm_device *);
114 static void tegra_encoder_destroy(struct drm_encoder *);
115
116 static const struct drm_encoder_funcs tegra_encoder_funcs = {
117 .destroy = tegra_encoder_destroy
118 };
119
120 static void tegra_encoder_dpms(struct drm_encoder *, int);
121 static bool tegra_encoder_mode_fixup(struct drm_encoder *,
122 const struct drm_display_mode *, struct drm_display_mode *);
123 static void tegra_encoder_mode_set(struct drm_encoder *,
124 struct drm_display_mode *, struct drm_display_mode *);
125 static void tegra_encoder_prepare(struct drm_encoder *);
126 static void tegra_encoder_commit(struct drm_encoder *);
127
128 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = {
129 .dpms = tegra_encoder_dpms,
130 .mode_fixup = tegra_encoder_mode_fixup,
131 .prepare = tegra_encoder_prepare,
132 .commit = tegra_encoder_commit,
133 .mode_set = tegra_encoder_mode_set
134 };
135
136 static int tegra_connector_init(struct drm_device *, struct drm_encoder *);
137 static void tegra_connector_destroy(struct drm_connector *);
138 static enum drm_connector_status tegra_connector_detect(struct drm_connector *,
139 bool);
140
141 static const struct drm_connector_funcs tegra_connector_funcs = {
142 .dpms = drm_helper_connector_dpms,
143 .detect = tegra_connector_detect,
144 .fill_modes = drm_helper_probe_single_connector_modes,
145 .destroy = tegra_connector_destroy
146 };
147
148 static int tegra_connector_mode_valid(struct drm_connector *,
149 struct drm_display_mode *);
150 static int tegra_connector_get_modes(struct drm_connector *);
151
152 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = {
153 .mode_valid = tegra_connector_mode_valid,
154 .get_modes = tegra_connector_get_modes,
155 };
156
157 static const struct tegra_hdmi_tmds_config {
158 u_int dot_clock;
159 uint32_t sor_pll0;
160 uint32_t sor_pll1;
161 uint32_t sor_lane_drive_current;
162 uint32_t pe_current;
163 uint32_t sor_io_peak_current;
164 uint32_t sor_pad_ctls0;
165 uint32_t car_plld_misc; /* XXX unused? */
166 } tegra_hdmi_tmds_config[] = {
167 /* 480p */
168 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f,
169 0x00000000, 0x03030303, 0x800034bb, 0x40400820 },
170 /* 720p / 1080i */
171 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c,
172 0x00000000, 0x07070707, 0x800034bb, 0x40400820 },
173 /* 1080p */
174 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d,
175 0x00000000, 0x05050505, 0x800034bb, 0x40400820 },
176 /* 2160p */
177 { 297000, 0x01003f10, 0x00300f00, 0x37373737,
178 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 },
179 };
180
181 int
tegra_drm_mode_init(struct drm_device * ddev)182 tegra_drm_mode_init(struct drm_device *ddev)
183 {
184 int error;
185
186 drm_mode_config_init(ddev);
187 ddev->mode_config.min_width = 0;
188 ddev->mode_config.min_height = 0;
189 ddev->mode_config.max_width = 4096;
190 ddev->mode_config.max_height = 2160;
191 ddev->mode_config.funcs = &tegra_mode_config_funcs;
192
193 error = tegra_crtc_init(ddev, 0);
194 if (error)
195 return error;
196
197 error = tegra_crtc_init(ddev, 1);
198 if (error)
199 return error;
200
201 error = tegra_encoder_init(ddev);
202 if (error)
203 return error;
204
205 error = drm_vblank_init(ddev, 2);
206 if (error)
207 return error;
208
209 return 0;
210 }
211
212 int
tegra_drm_framebuffer_init(struct drm_device * ddev,struct tegra_framebuffer * fb)213 tegra_drm_framebuffer_init(struct drm_device *ddev,
214 struct tegra_framebuffer *fb)
215 {
216 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs);
217 }
218
219 static struct drm_framebuffer *
tegra_fb_create(struct drm_device * ddev,struct drm_file * file,const struct drm_mode_fb_cmd2 * cmd)220 tegra_fb_create(struct drm_device *ddev, struct drm_file *file,
221 const struct drm_mode_fb_cmd2 *cmd)
222 {
223 struct tegra_framebuffer *fb;
224 struct drm_gem_object *gem_obj;
225 int error;
226
227 if (cmd->flags)
228 return NULL;
229 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 &&
230 cmd->pixel_format != DRM_FORMAT_XRGB8888) {
231 return NULL;
232 }
233
234 gem_obj = drm_gem_object_lookup(file, cmd->handles[0]);
235 if (gem_obj == NULL)
236 return NULL;
237
238 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP);
239 drm_helper_mode_fill_fb_struct(ddev, &fb->base, cmd);
240 fb->obj = to_drm_gem_cma_obj(gem_obj);
241
242 error = tegra_drm_framebuffer_init(ddev, fb);
243 if (error)
244 goto dealloc;
245
246 return &fb->base;
247
248 drm_framebuffer_cleanup(&fb->base);
249 dealloc:
250 kmem_free(fb, sizeof(*fb));
251 drm_gem_object_put_unlocked(gem_obj);
252
253 return NULL;
254 }
255
256 static int
tegra_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file,unsigned int * handle)257 tegra_framebuffer_create_handle(struct drm_framebuffer *fb,
258 struct drm_file *file, unsigned int *handle)
259 {
260 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb);
261
262 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle);
263 }
264
265 static void
tegra_framebuffer_destroy(struct drm_framebuffer * fb)266 tegra_framebuffer_destroy(struct drm_framebuffer *fb)
267 {
268 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb);
269
270 drm_framebuffer_cleanup(fb);
271 drm_gem_object_put_unlocked(&tegra_fb->obj->base);
272 kmem_free(tegra_fb, sizeof(*tegra_fb));
273 }
274
275 static int
tegra_crtc_init(struct drm_device * ddev,int index)276 tegra_crtc_init(struct drm_device *ddev, int index)
277 {
278 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
279 struct tegra_crtc *crtc;
280 bus_addr_t offset;
281 bus_size_t size;
282 u_int intr;
283 int error;
284
285 if (sc->sc_clk_dc[index] == NULL ||
286 sc->sc_clk_hdmi_parent == NULL ||
287 sc->sc_rst_dc[index] == NULL) {
288 DRM_ERROR("no clocks configured for crtc %d\n", index);
289 return -EIO;
290 }
291
292 switch (index) {
293 case 0:
294 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET;
295 size = TEGRA_DISPLAYA_SIZE;
296 intr = TEGRA_INTR_DISPLAYA;
297 break;
298 case 1:
299 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET;
300 size = TEGRA_DISPLAYB_SIZE;
301 intr = TEGRA_INTR_DISPLAYB;
302 break;
303 default:
304 return -EINVAL;
305 }
306
307 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP);
308 crtc->index = index;
309 crtc->bst = sc->sc_bst;
310 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh);
311 if (error) {
312 kmem_free(crtc, sizeof(*crtc));
313 return -error;
314 }
315 crtc->size = size;
316 crtc->intr = intr;
317 crtc->ih = intr_establish_xname(intr, IPL_VM, IST_LEVEL | IST_MPSAFE,
318 tegra_crtc_intr, crtc, device_xname(sc->sc_dev)); /* XXX */
319 if (crtc->ih == NULL) {
320 DRM_ERROR("failed to establish interrupt for crtc %d\n", index);
321 }
322 const size_t cursor_size = 256 * 256 * 4;
323 crtc->cursor_obj = drm_gem_cma_create(ddev, cursor_size);
324 if (crtc->cursor_obj == NULL) {
325 kmem_free(crtc, sizeof(*crtc));
326 return -ENOMEM;
327 }
328
329 /* Enter reset */
330 fdtbus_reset_assert(sc->sc_rst_dc[index]);
331
332 /* Turn on power to display partition */
333 const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB;
334 tegra_pmc_power(pmc_partid, true);
335 tegra_pmc_remove_clamping(pmc_partid);
336
337 /* Set parent clock to the HDMI parent (ignoring DC parent in DT!) */
338 error = clk_set_parent(sc->sc_clk_dc[index],
339 sc->sc_clk_hdmi_parent);
340 if (error) {
341 DRM_ERROR("failed to set crtc %d clock parent: %d\n",
342 index, error);
343 return -error;
344 }
345
346 /* Enable DC clock */
347 error = clk_enable(sc->sc_clk_dc[index]);
348 if (error) {
349 DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error);
350 return -error;
351 }
352
353 /* Leave reset */
354 fdtbus_reset_deassert(sc->sc_rst_dc[index]);
355
356 crtc->clk_parent = sc->sc_clk_hdmi_parent;
357
358 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK);
359
360 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs);
361 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs);
362
363 return 0;
364 }
365
366 static int
tegra_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height)367 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
368 uint32_t handle, uint32_t width, uint32_t height)
369 {
370 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
371 struct drm_gem_object *gem_obj = NULL;
372 struct drm_gem_cma_object *obj;
373 uint32_t cfg, opt;
374 int error;
375
376 if (tegra_crtc->enabled == false)
377 return 0;
378
379 if (handle == 0) {
380 /* hide cursor */
381 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
382 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) {
383 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE;
384 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
385 /* Commit settings */
386 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
387 DC_CMD_STATE_CONTROL_GENERAL_UPDATE);
388 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
389 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ);
390 }
391 error = 0;
392 goto done;
393 }
394
395 if ((width != height) ||
396 (width != 32 && width != 64 && width != 128 && width != 256)) {
397 DRM_ERROR("Cursor dimension %ux%u not supported\n",
398 width, height);
399 error = -EINVAL;
400 goto done;
401 }
402
403 gem_obj = drm_gem_object_lookup(file_priv, handle);
404 if (gem_obj == NULL) {
405 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n",
406 handle, tegra_crtc->index);
407 error = -ENOENT;
408 goto done;
409 }
410 obj = to_drm_gem_cma_obj(gem_obj);
411
412 if (obj->base.size < width * height * 4) {
413 DRM_ERROR("Cursor buffer is too small\n");
414 error = -ENOMEM;
415 goto done;
416 }
417
418 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY,
419 DC_DISP_CURSOR_START_ADDR_CLIPPING);
420 switch (width) {
421 case 32:
422 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32,
423 DC_DISP_CURSOR_START_ADDR_SIZE);
424 break;
425 case 64:
426 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64,
427 DC_DISP_CURSOR_START_ADDR_SIZE);
428 break;
429 case 128:
430 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128,
431 DC_DISP_CURSOR_START_ADDR_SIZE);
432 break;
433 case 256:
434 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256,
435 DC_DISP_CURSOR_START_ADDR_SIZE);
436 break;
437 }
438
439 /* copy cursor (argb -> rgba) */
440 struct drm_gem_cma_object *cursor_obj = tegra_crtc->cursor_obj;
441 uint32_t off, *cp = obj->vaddr, *crtc_cp = cursor_obj->vaddr;
442 for (off = 0; off < width * height; off++) {
443 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24);
444 }
445
446 const uint64_t paddr = cursor_obj->dmasegs[0].ds_addr;
447
448 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG,
449 (paddr >> 32) & 3);
450 cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff,
451 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO);
452 const uint32_t ocfg =
453 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG);
454 if (cfg != ocfg) {
455 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg);
456 }
457
458 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG);
459 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL;
460 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL);
461 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL;
462 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL);
463 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA;
464 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA);
465 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL;
466 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg);
467
468 /* set cursor position */
469 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
470 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) |
471 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V));
472
473 /* Commit settings */
474 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
475 DC_CMD_STATE_CONTROL_CURSOR_UPDATE);
476 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
477 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ);
478
479 /* show cursor */
480 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
481 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) {
482 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE;
483 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
484
485 /* Commit settings */
486 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
487 DC_CMD_STATE_CONTROL_GENERAL_UPDATE);
488 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
489 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ);
490 }
491
492 error = 0;
493
494 done:
495 if (error == 0) {
496 /* Wait for activation request to complete */
497 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) &
498 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ)
499 ;
500 }
501
502 if (gem_obj) {
503 drm_gem_object_put_unlocked(gem_obj);
504 }
505
506 return error;
507 }
508
509 static int
tegra_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)510 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
511 {
512 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
513
514 tegra_crtc->cursor_x = x & 0x3fff;
515 tegra_crtc->cursor_y = y & 0x3fff;
516
517 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
518 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) |
519 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V));
520
521 /* Commit settings */
522 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
523 DC_CMD_STATE_CONTROL_CURSOR_UPDATE);
524 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
525 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ);
526
527 return 0;
528 }
529
530 static void
tegra_crtc_destroy(struct drm_crtc * crtc)531 tegra_crtc_destroy(struct drm_crtc *crtc)
532 {
533 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
534 drm_crtc_cleanup(crtc);
535 if (tegra_crtc->ih) {
536 intr_disestablish(tegra_crtc->ih);
537 }
538 drm_gem_cma_free_object(&tegra_crtc->cursor_obj->base);
539 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size);
540 kmem_free(tegra_crtc, sizeof(*tegra_crtc));
541 }
542
543 static void
tegra_crtc_dpms(struct drm_crtc * crtc,int mode)544 tegra_crtc_dpms(struct drm_crtc *crtc, int mode)
545 {
546 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
547
548 switch (mode) {
549 case DRM_MODE_DPMS_ON:
550 case DRM_MODE_DPMS_STANDBY:
551 case DRM_MODE_DPMS_SUSPEND:
552 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
553 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0);
554 break;
555 case DRM_MODE_DPMS_OFF:
556 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
557 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE);
558 break;
559 }
560 }
561
562 static bool
tegra_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)563 tegra_crtc_mode_fixup(struct drm_crtc *crtc,
564 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
565 {
566 return true;
567 }
568
569 static int
tegra_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)570 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
571 struct drm_display_mode *adjusted_mode, int x, int y,
572 struct drm_framebuffer *old_fb)
573 {
574 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
575 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start;
576 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end;
577 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;
578 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start;
579 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
580 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay;
581
582 /* Set colour depth to ARGB8888 */
583 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG,
584 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8,
585 DC_WINC_A_COLOR_DEPTH_DEPTH));
586
587 /* Disable byte swapping */
588 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG,
589 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP,
590 DC_WINC_A_BYTE_SWAP_SWAP));
591
592 /* Initial DDA */
593 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0);
594 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0);
595 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000);
596
597 /* Window position, size, stride */
598 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG,
599 __SHIFTIN(0, DC_WINC_A_POSITION_V) |
600 __SHIFTIN(0, DC_WINC_A_POSITION_H));
601 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG,
602 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) |
603 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H));
604 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG,
605 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) |
606 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8),
607 DC_WINC_A_PRESCALED_SIZE_H));
608 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG,
609 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8),
610 DC_WINC_A_LINE_STRIDE_LINE_STRIDE));
611
612 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0);
613
614 /* Enable window A */
615 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
616 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE);
617
618 /* Timing and signal options */
619 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG,
620 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS));
621 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG,
622 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888,
623 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE));
624 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG,
625 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE);
626 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG,
627 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE,
628 DC_DISP_H_PULSE2_CONTROL_V_QUAL) |
629 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A,
630 DC_DISP_H_PULSE2_CONTROL_LAST));
631
632 const u_int pulse_start = 1 + hspw + hbp - 10;
633 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG,
634 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) |
635 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END));
636
637 /* Pixel clock */
638 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent);
639 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2;
640 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG,
641 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) |
642 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER));
643
644 /* Mode timings */
645 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG,
646 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) |
647 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H));
648 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG,
649 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) |
650 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H));
651 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG,
652 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) |
653 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H));
654 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG,
655 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) |
656 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H));
657 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG,
658 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) |
659 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H));
660
661 return 0;
662 }
663
664 static int
tegra_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)665 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb,
666 int x, int y, int atomic)
667 {
668 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
669 struct tegra_framebuffer *tegra_fb = atomic ?
670 to_tegra_framebuffer(fb) :
671 to_tegra_framebuffer(crtc->primary->fb);
672
673 uint64_t paddr = (uint64_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr;
674
675 /* Framebuffer start address */
676 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3);
677 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff);
678
679 /* Offsets */
680 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x);
681 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y);
682
683 /* Surface kind */
684 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG,
685 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH,
686 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND));
687
688 return 0;
689 }
690
691 static int
tegra_crtc_mode_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)692 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
693 struct drm_framebuffer *old_fb)
694 {
695 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
696
697 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0);
698
699 /* Commit settings */
700 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
701 DC_CMD_STATE_CONTROL_WIN_A_UPDATE);
702 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
703 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ);
704
705 return 0;
706 }
707
708 static int
tegra_crtc_mode_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)709 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
710 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state)
711 {
712 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
713
714 tegra_crtc_do_set_base(crtc, fb, x, y, 1);
715
716 /* Commit settings */
717 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
718 DC_CMD_STATE_CONTROL_WIN_A_UPDATE);
719 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
720 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ);
721
722 return 0;
723 }
724
725 static void
tegra_crtc_disable(struct drm_crtc * crtc)726 tegra_crtc_disable(struct drm_crtc *crtc)
727 {
728 }
729
730 static void
tegra_crtc_prepare(struct drm_crtc * crtc)731 tegra_crtc_prepare(struct drm_crtc *crtc)
732 {
733 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
734
735 /* Access control */
736 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0);
737
738 /* Enable window A programming */
739 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG,
740 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT);
741 }
742
743 static void
tegra_crtc_commit(struct drm_crtc * crtc)744 tegra_crtc_commit(struct drm_crtc *crtc)
745 {
746 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
747
748 /* Enable continuous display mode */
749 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG,
750 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY,
751 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE));
752
753 /* Enable power */
754 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG,
755 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE |
756 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE |
757 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE |
758 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE |
759 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE |
760 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE |
761 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE,
762 0);
763
764 /* Commit settings */
765 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
766 DC_CMD_STATE_CONTROL_GENERAL_UPDATE |
767 DC_CMD_STATE_CONTROL_WIN_A_UPDATE);
768 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
769 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ |
770 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ);
771
772 tegra_crtc->enabled = true;
773 }
774
775 static int
tegra_encoder_init(struct drm_device * ddev)776 tegra_encoder_init(struct drm_device *ddev)
777 {
778 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
779 struct tegra_encoder *encoder;
780 int error;
781
782 if (sc->sc_clk_hdmi == NULL ||
783 sc->sc_clk_hdmi_parent == NULL ||
784 sc->sc_rst_hdmi == NULL) {
785 DRM_ERROR("no clocks configured for hdmi\n");
786 DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent);
787 DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi);
788 return -EIO;
789 }
790
791 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET;
792 const bus_size_t size = TEGRA_HDMI_SIZE;
793
794 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP);
795 encoder->bst = sc->sc_bst;
796 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh);
797 if (error) {
798 kmem_free(encoder, sizeof(*encoder));
799 return -error;
800 }
801 encoder->size = size;
802
803 tegra_pmc_hdmi_enable();
804
805 /* Enable parent PLL */
806 error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000);
807 if (error) {
808 DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error);
809 return -error;
810 }
811 error = clk_enable(sc->sc_clk_hdmi_parent);
812 if (error) {
813 DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error);
814 return -error;
815 }
816
817 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs,
818 DRM_MODE_ENCODER_TMDS, NULL);
819 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs);
820
821 encoder->base.possible_crtcs = (1 << 0) | (1 << 1);
822
823 return tegra_connector_init(ddev, &encoder->base);
824 }
825
826 static void
tegra_encoder_destroy(struct drm_encoder * encoder)827 tegra_encoder_destroy(struct drm_encoder *encoder)
828 {
829 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder);
830 drm_encoder_cleanup(encoder);
831 kmem_free(tegra_encoder, sizeof(*tegra_encoder));
832 }
833
834 static void
tegra_encoder_dpms(struct drm_encoder * encoder,int mode)835 tegra_encoder_dpms(struct drm_encoder *encoder, int mode)
836 {
837 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder);
838
839 if (encoder->crtc == NULL)
840 return;
841
842 switch (mode) {
843 case DRM_MODE_DPMS_ON:
844 case DRM_MODE_DPMS_STANDBY:
845 case DRM_MODE_DPMS_SUSPEND:
846 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG,
847 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE);
848 break;
849 case DRM_MODE_DPMS_OFF:
850 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG,
851 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0);
852 break;
853 }
854 }
855
856 static bool
tegra_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)857 tegra_encoder_mode_fixup(struct drm_encoder *encoder,
858 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
859 {
860 return true;
861 }
862
863 static int
tegra_encoder_hdmi_set_clock(struct drm_encoder * encoder,u_int rate)864 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate)
865 {
866 struct drm_device *ddev = encoder->dev;
867 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
868 int error;
869
870 /* Enter reset */
871 fdtbus_reset_assert(sc->sc_rst_hdmi);
872
873 /* Set HDMI parent clock */
874 error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent);
875 if (error) {
876 DRM_ERROR("couldn't set hdmi parent: %d\n", error);
877 return -error;
878 }
879
880 /* Set dot clock frequency */
881 error = clk_set_rate(sc->sc_clk_hdmi, rate);
882 if (error) {
883 DRM_ERROR("couldn't set hdmi clock: %d\n", error);
884 return -error;
885 }
886 error = clk_enable(sc->sc_clk_hdmi);
887 if (error) {
888 DRM_ERROR("couldn't enable hdmi clock: %d\n", error);
889 return -error;
890 }
891
892 /* Leave reset */
893 fdtbus_reset_deassert(sc->sc_rst_hdmi);
894
895 return 0;
896 }
897
898 static void
tegra_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)899 tegra_encoder_mode_set(struct drm_encoder *encoder,
900 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
901 {
902 struct drm_device *ddev = encoder->dev;
903 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder);
904 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc);
905 struct tegra_connector *tegra_connector = NULL;
906 struct drm_connector *connector;
907 const struct tegra_hdmi_tmds_config *tmds = NULL;
908 uint32_t input_ctrl;
909 int retry;
910 u_int i;
911
912 tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000);
913
914 /* find the connector for this encoder */
915 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
916 if (connector->encoder == encoder) {
917 tegra_connector = to_tegra_connector(connector);
918 break;
919 }
920 }
921
922 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) {
923 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) {
924 break;
925 }
926 }
927 if (i < __arraycount(tegra_hdmi_tmds_config)) {
928 tmds = &tegra_hdmi_tmds_config[i];
929 } else {
930 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1];
931 }
932
933 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);
934 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);
935 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,
936 tmds->sor_lane_drive_current);
937 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG,
938 tmds->pe_current);
939 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,
940 tmds->sor_io_peak_current);
941 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,
942 tmds->sor_pad_ctls0);
943
944 const u_int div = (mode->crtc_clock / 1000) * 4;
945 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG,
946 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) |
947 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC));
948
949 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG,
950 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS,
951 HDMI_NV_PDISP_SOR_CSTM_MODE) |
952 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) |
953 HDMI_NV_PDISP_SOR_CSTM_PLLDIV,
954 HDMI_NV_PDISP_SOR_CSTM_MODE |
955 HDMI_NV_PDISP_SOR_CSTM_ROTCLK |
956 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN);
957
958 const uint32_t inst =
959 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO |
960 HDMI_NV_PDISP_SOR_SEQ_INST_HALT |
961 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) |
962 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME);
963 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst);
964 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst);
965
966 input_ctrl = __SHIFTIN(tegra_crtc->index,
967 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT);
968 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480)
969 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE;
970 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl);
971
972 /* Start SOR */
973 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG,
974 0,
975 HDMI_NV_PDISP_SOR_PLL0_PWR |
976 HDMI_NV_PDISP_SOR_PLL0_VCOPD |
977 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN);
978 delay(10);
979 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG,
980 0,
981 HDMI_NV_PDISP_SOR_PLL0_PDBG);
982
983 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG,
984 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE |
985 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW);
986
987 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG,
988 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE);
989
990 for (retry = 10000; retry > 0; retry--) {
991 const uint32_t pwr = HDMI_READ(tegra_encoder,
992 HDMI_NV_PDISP_SOR_PWR_REG);
993 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0)
994 break;
995 delay(10);
996 }
997 if (retry == 0) {
998 DRM_ERROR("timeout enabling SOR power\n");
999 }
1000
1001 uint32_t state2 =
1002 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) |
1003 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) |
1004 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) |
1005 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL);
1006 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1007 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL;
1008 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1009 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL;
1010 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2);
1011
1012 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG,
1013 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE,
1014 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) |
1015 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE);
1016
1017 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
1018
1019 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG,
1020 HDMI_NV_PDISP_SOR_STATE0_UPDATE);
1021
1022 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG,
1023 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0);
1024
1025 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
1026
1027 const u_int rekey = 56;
1028 const u_int hspw = mode->hsync_end - mode->hsync_start;
1029 const u_int hbp = mode->htotal - mode->hsync_end;
1030 const u_int hfp = mode->hsync_start - mode->hdisplay;
1031 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32;
1032 uint32_t ctrl =
1033 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) |
1034 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET);
1035 if (tegra_connector && tegra_connector->has_hdmi_sink) {
1036 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */
1037 }
1038 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl);
1039
1040 if (tegra_connector && tegra_connector->has_hdmi_sink &&
1041 tegra_connector->has_audio) {
1042 struct hdmi_audio_infoframe ai;
1043 struct hdmi_avi_infoframe avii;
1044 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1045 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1046 const u_int n = 6144; /* 48 kHz */
1047 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480;
1048
1049 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG,
1050 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
1051 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) |
1052 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL);
1053 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG,
1054 HDMI_NV_PDISP_AUDIO_N_RESETF |
1055 HDMI_NV_PDISP_AUDIO_N_GENERATE |
1056 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE));
1057
1058 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG,
1059 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS |
1060 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS |
1061 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL));
1062
1063 /*
1064 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by
1065 * software in the 44.1 kHz register regardless of chosen rate.
1066 */
1067 HDMI_WRITE(tegra_encoder,
1068 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG,
1069 cts << 8);
1070 HDMI_WRITE(tegra_encoder,
1071 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG,
1072 0x80000000 | n);
1073
1074 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0,
1075 HDMI_NV_PDISP_AUDIO_N_RESETF);
1076
1077 HDMI_WRITE(tegra_encoder,
1078 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000);
1079
1080 hdmi_audio_infoframe_init(&ai);
1081 ai.channels = 2;
1082 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf));
1083 HDMI_WRITE(tegra_encoder,
1084 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG,
1085 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16));
1086 HDMI_WRITE(tegra_encoder,
1087 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG,
1088 aibuf[3] | (aibuf[4] << 8) |
1089 (aibuf[5] << 16) | (aibuf[6] << 24));
1090 HDMI_WRITE(tegra_encoder,
1091 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG,
1092 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16));
1093
1094 hdmi_avi_infoframe_init(&avii);
1095 drm_hdmi_avi_infoframe_from_display_mode(&avii, connector,
1096 mode);
1097 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf));
1098 HDMI_WRITE(tegra_encoder,
1099 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG,
1100 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16));
1101 HDMI_WRITE(tegra_encoder,
1102 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG,
1103 aviibuf[3] | (aviibuf[4] << 8) |
1104 (aviibuf[5] << 16) | (aviibuf[6] << 24));
1105 HDMI_WRITE(tegra_encoder,
1106 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG,
1107 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16));
1108 HDMI_WRITE(tegra_encoder,
1109 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG,
1110 aviibuf[10] | (aviibuf[11] << 8) |
1111 (aviibuf[12] << 16) | (aviibuf[13] << 24));
1112 HDMI_WRITE(tegra_encoder,
1113 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG,
1114 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16));
1115
1116 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG,
1117 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO);
1118 HDMI_WRITE(tegra_encoder,
1119 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG,
1120 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE);
1121 HDMI_WRITE(tegra_encoder,
1122 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG,
1123 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE);
1124 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
1125 } else {
1126 HDMI_WRITE(tegra_encoder,
1127 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0);
1128 HDMI_WRITE(tegra_encoder,
1129 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
1130 HDMI_WRITE(tegra_encoder,
1131 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0);
1132 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
1133 }
1134
1135 /* Enable DC output to HDMI */
1136 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG,
1137 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0);
1138
1139 /* Commit settings */
1140 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
1141 DC_CMD_STATE_CONTROL_GENERAL_UPDATE |
1142 DC_CMD_STATE_CONTROL_WIN_A_UPDATE);
1143 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
1144 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ |
1145 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ);
1146 }
1147
1148 static void
tegra_encoder_prepare(struct drm_encoder * encoder)1149 tegra_encoder_prepare(struct drm_encoder *encoder)
1150 {
1151 }
1152
1153 static void
tegra_encoder_commit(struct drm_encoder * encoder)1154 tegra_encoder_commit(struct drm_encoder *encoder)
1155 {
1156 }
1157
1158 static int
tegra_connector_init(struct drm_device * ddev,struct drm_encoder * encoder)1159 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder)
1160 {
1161 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
1162 struct tegra_connector *connector;
1163
1164 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP);
1165
1166 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs,
1167 DRM_MODE_CONNECTOR_HDMIA);
1168 drm_connector_helper_add(&connector->base,
1169 &tegra_connector_helper_funcs);
1170
1171 connector->base.interlace_allowed = 0;
1172 connector->base.doublescan_allowed = 0;
1173
1174 drm_sysfs_connector_add(&connector->base);
1175
1176 connector->base.polled =
1177 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
1178
1179 drm_connector_attach_encoder(&connector->base, encoder);
1180
1181 connector->hpd = sc->sc_pin_hpd;
1182 if (!connector->hpd)
1183 DRM_ERROR("failed to find hpd pin for connector\n");
1184
1185 connector->ddc = sc->sc_ddc;
1186 if (!connector->ddc)
1187 DRM_ERROR("failed to find ddc device for connector\n");
1188
1189 return drm_connector_register(&connector->base);
1190 }
1191
1192 static void
tegra_connector_destroy(struct drm_connector * connector)1193 tegra_connector_destroy(struct drm_connector *connector)
1194 {
1195 struct tegra_connector *tegra_connector = to_tegra_connector(connector);
1196
1197 drm_sysfs_connector_remove(connector);
1198 drm_connector_cleanup(connector);
1199 kmem_free(tegra_connector, sizeof(*tegra_connector));
1200 }
1201
1202 static enum drm_connector_status
tegra_connector_detect(struct drm_connector * connector,bool force)1203 tegra_connector_detect(struct drm_connector *connector, bool force)
1204 {
1205 struct tegra_connector *tegra_connector = to_tegra_connector(connector);
1206 bool con;
1207
1208
1209 if (!tegra_connector->hpd) {
1210 tegra_connector->has_hdmi_sink = false;
1211 tegra_connector->has_audio = false;
1212 return connector_status_connected;
1213 }
1214
1215 con = fdtbus_gpio_read(tegra_connector->hpd);
1216 if (con) {
1217 return connector_status_connected;
1218 } else {
1219 prop_dictionary_t prop = device_properties(connector->dev->dev);
1220 prop_dictionary_remove(prop, "physical-address");
1221 tegra_connector->has_hdmi_sink = false;
1222 tegra_connector->has_audio = false;
1223 return connector_status_disconnected;
1224 }
1225 }
1226
1227 static int
tegra_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1228 tegra_connector_mode_valid(struct drm_connector *connector,
1229 struct drm_display_mode *mode)
1230 {
1231 return MODE_OK;
1232 }
1233
1234 static int
tegra_connector_get_modes(struct drm_connector * connector)1235 tegra_connector_get_modes(struct drm_connector *connector)
1236 {
1237 struct tegra_connector *tegra_connector = to_tegra_connector(connector);
1238 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev);
1239 prop_dictionary_t prop = device_properties(connector->dev->dev);
1240 char edid[EDID_LENGTH * 4];
1241 struct edid *pedid = NULL;
1242 int error, block;
1243
1244 if (tegra_connector->ddc) {
1245 memset(edid, 0, sizeof(edid));
1246 for (block = 0; block < 4; block++) {
1247 error = ddc_read_edid_block(tegra_connector->ddc,
1248 &edid[block * EDID_LENGTH], EDID_LENGTH, block);
1249 if (error)
1250 break;
1251 if (block == 0) {
1252 pedid = (struct edid *)edid;
1253 if (edid[0x7e] == 0)
1254 break;
1255 }
1256 }
1257 }
1258
1259 if (pedid) {
1260 if (sc->sc_force_dvi) {
1261 tegra_connector->has_hdmi_sink = false;
1262 tegra_connector->has_audio = false;
1263 } else {
1264 tegra_connector->has_hdmi_sink =
1265 drm_detect_hdmi_monitor(pedid);
1266 tegra_connector->has_audio =
1267 drm_detect_monitor_audio(pedid);
1268 }
1269 drm_connector_update_edid_property(connector, pedid);
1270 error = drm_add_edid_modes(connector, pedid);
1271 if (drm_detect_hdmi_monitor(pedid)) {
1272 prop_dictionary_set_uint16(prop, "physical-address",
1273 connector->physical_address);
1274 }
1275 return error;
1276 } else {
1277 drm_connector_update_edid_property(connector, NULL);
1278 return 0;
1279 }
1280 }
1281
1282 static int
tegra_crtc_intr(void * priv)1283 tegra_crtc_intr(void *priv)
1284 {
1285 struct tegra_crtc *tegra_crtc = priv;
1286 struct drm_device *ddev = tegra_crtc->base.dev;
1287 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
1288 int rv = 0;
1289
1290 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG);
1291
1292 if (status & DC_CMD_INT_V_BLANK) {
1293 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
1294 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]);
1295 drm_handle_vblank(ddev, tegra_crtc->index);
1296 rv = 1;
1297 }
1298
1299 return rv;
1300 }
1301
1302 u32
tegra_drm_get_vblank_counter(struct drm_device * ddev,unsigned int crtc)1303 tegra_drm_get_vblank_counter(struct drm_device *ddev, unsigned int crtc)
1304 {
1305 struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
1306
1307 if (crtc > 1)
1308 return 0;
1309
1310 return sc->sc_vbl_received[crtc];
1311 }
1312
1313 int
tegra_drm_enable_vblank(struct drm_device * ddev,unsigned int crtc)1314 tegra_drm_enable_vblank(struct drm_device *ddev, unsigned int crtc)
1315 {
1316 struct tegra_crtc *tegra_crtc = NULL;
1317 struct drm_crtc *iter;
1318
1319 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) {
1320 if (to_tegra_crtc(iter)->index == crtc) {
1321 tegra_crtc = to_tegra_crtc(iter);
1322 break;
1323 }
1324 }
1325 if (tegra_crtc == NULL)
1326 return -EINVAL;
1327
1328 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0);
1329
1330 return 0;
1331 }
1332
1333 void
tegra_drm_disable_vblank(struct drm_device * ddev,unsigned int crtc)1334 tegra_drm_disable_vblank(struct drm_device *ddev, unsigned int crtc)
1335 {
1336 struct tegra_crtc *tegra_crtc = NULL;
1337 struct drm_crtc *iter;
1338
1339 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) {
1340 if (to_tegra_crtc(iter)->index == crtc) {
1341 tegra_crtc = to_tegra_crtc(iter);
1342 break;
1343 }
1344 }
1345 if (tegra_crtc == NULL)
1346 return;
1347
1348 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK);
1349 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
1350 }
1351