1 /* $NetBSD: tegra_drm_mode.c,v 1.10 2015/12/13 17:39:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.10 2015/12/13 17:39:19 jmcneill Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <dev/i2c/ddcvar.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_intr.h> 42 #include <arm/nvidia/tegra_dcreg.h> 43 #include <arm/nvidia/tegra_hdmireg.h> 44 #include <arm/nvidia/tegra_drm.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 static struct drm_framebuffer *tegra_fb_create(struct drm_device *, 49 struct drm_file *, struct drm_mode_fb_cmd2 *); 50 51 static const struct drm_mode_config_funcs tegra_mode_config_funcs = { 52 .fb_create = tegra_fb_create 53 }; 54 55 static int tegra_framebuffer_create_handle(struct drm_framebuffer *, 56 struct drm_file *, unsigned int *); 57 static void tegra_framebuffer_destroy(struct drm_framebuffer *); 58 59 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = { 60 .create_handle = tegra_framebuffer_create_handle, 61 .destroy = tegra_framebuffer_destroy 62 }; 63 64 static int tegra_crtc_init(struct drm_device *, int); 65 static void tegra_crtc_destroy(struct drm_crtc *); 66 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *, 67 uint32_t, uint32_t, uint32_t); 68 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int); 69 static int tegra_crtc_intr(void *); 70 71 static const struct drm_crtc_funcs tegra_crtc_funcs = { 72 .cursor_set = tegra_crtc_cursor_set, 73 .cursor_move = tegra_crtc_cursor_move, 74 .set_config = drm_crtc_helper_set_config, 75 .destroy = tegra_crtc_destroy 76 }; 77 78 static void tegra_crtc_dpms(struct drm_crtc *, int); 79 static bool tegra_crtc_mode_fixup(struct drm_crtc *, 80 const struct drm_display_mode *, 81 struct drm_display_mode *); 82 static int tegra_crtc_mode_set(struct drm_crtc *, 83 struct drm_display_mode *, struct drm_display_mode *, 84 int, int, struct drm_framebuffer *); 85 static int tegra_crtc_mode_set_base(struct drm_crtc *, 86 int, int, struct drm_framebuffer *); 87 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *, 88 struct drm_framebuffer *, int, int, enum mode_set_atomic); 89 static void tegra_crtc_disable(struct drm_crtc *); 90 static void tegra_crtc_prepare(struct drm_crtc *); 91 static void tegra_crtc_commit(struct drm_crtc *); 92 93 static int tegra_crtc_do_set_base(struct drm_crtc *, 94 struct drm_framebuffer *, int, int, int); 95 96 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 97 .dpms = tegra_crtc_dpms, 98 .mode_fixup = tegra_crtc_mode_fixup, 99 .mode_set = tegra_crtc_mode_set, 100 .mode_set_base = tegra_crtc_mode_set_base, 101 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic, 102 .disable = tegra_crtc_disable, 103 .prepare = tegra_crtc_prepare, 104 .commit = tegra_crtc_commit 105 }; 106 107 static int tegra_encoder_init(struct drm_device *); 108 static void tegra_encoder_destroy(struct drm_encoder *); 109 110 static const struct drm_encoder_funcs tegra_encoder_funcs = { 111 .destroy = tegra_encoder_destroy 112 }; 113 114 static void tegra_encoder_dpms(struct drm_encoder *, int); 115 static bool tegra_encoder_mode_fixup(struct drm_encoder *, 116 const struct drm_display_mode *, struct drm_display_mode *); 117 static void tegra_encoder_mode_set(struct drm_encoder *, 118 struct drm_display_mode *, struct drm_display_mode *); 119 static void tegra_encoder_prepare(struct drm_encoder *); 120 static void tegra_encoder_commit(struct drm_encoder *); 121 122 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = { 123 .dpms = tegra_encoder_dpms, 124 .mode_fixup = tegra_encoder_mode_fixup, 125 .prepare = tegra_encoder_prepare, 126 .commit = tegra_encoder_commit, 127 .mode_set = tegra_encoder_mode_set 128 }; 129 130 static int tegra_connector_init(struct drm_device *, struct drm_encoder *); 131 static void tegra_connector_destroy(struct drm_connector *); 132 static enum drm_connector_status tegra_connector_detect(struct drm_connector *, 133 bool); 134 135 static const struct drm_connector_funcs tegra_connector_funcs = { 136 .dpms = drm_helper_connector_dpms, 137 .detect = tegra_connector_detect, 138 .fill_modes = drm_helper_probe_single_connector_modes, 139 .destroy = tegra_connector_destroy 140 }; 141 142 static int tegra_connector_mode_valid(struct drm_connector *, 143 struct drm_display_mode *); 144 static int tegra_connector_get_modes(struct drm_connector *); 145 static struct drm_encoder *tegra_connector_best_encoder(struct drm_connector *); 146 147 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = { 148 .mode_valid = tegra_connector_mode_valid, 149 .get_modes = tegra_connector_get_modes, 150 .best_encoder = tegra_connector_best_encoder 151 }; 152 153 static const struct tegra_hdmi_tmds_config { 154 u_int dot_clock; 155 uint32_t sor_pll0; 156 uint32_t sor_pll1; 157 uint32_t sor_lane_drive_current; 158 uint32_t pe_current; 159 uint32_t sor_io_peak_current; 160 uint32_t sor_pad_ctls0; 161 uint32_t car_plld_misc; /* XXX unused? */ 162 } tegra_hdmi_tmds_config[] = { 163 /* 480p */ 164 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 165 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 166 /* 720p / 1080i */ 167 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 168 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 169 /* 1080p */ 170 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 171 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 172 /* 2160p */ 173 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 174 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 175 }; 176 177 int 178 tegra_drm_mode_init(struct drm_device *ddev) 179 { 180 int error; 181 182 drm_mode_config_init(ddev); 183 ddev->mode_config.min_width = 0; 184 ddev->mode_config.min_height = 0; 185 ddev->mode_config.max_width = 4096; 186 ddev->mode_config.max_height = 2160; 187 ddev->mode_config.funcs = &tegra_mode_config_funcs; 188 189 error = tegra_crtc_init(ddev, 0); 190 if (error) 191 return error; 192 193 error = tegra_crtc_init(ddev, 1); 194 if (error) 195 return error; 196 197 error = tegra_encoder_init(ddev); 198 if (error) 199 return error; 200 201 error = drm_vblank_init(ddev, 2); 202 if (error) 203 return error; 204 205 return 0; 206 } 207 208 int 209 tegra_drm_framebuffer_init(struct drm_device *ddev, 210 struct tegra_framebuffer *fb) 211 { 212 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs); 213 } 214 215 static struct drm_framebuffer * 216 tegra_fb_create(struct drm_device *ddev, struct drm_file *file, 217 struct drm_mode_fb_cmd2 *cmd) 218 { 219 struct tegra_framebuffer *fb; 220 struct drm_gem_object *gem_obj; 221 int error; 222 223 if (cmd->flags) 224 return NULL; 225 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 && 226 cmd->pixel_format != DRM_FORMAT_XRGB8888) { 227 return NULL; 228 } 229 230 gem_obj = drm_gem_object_lookup(ddev, file, cmd->handles[0]); 231 if (gem_obj == NULL) 232 return NULL; 233 234 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP); 235 if (fb == NULL) 236 goto unref; 237 238 fb->obj = to_tegra_gem_obj(gem_obj); 239 fb->base.pitches[0] = cmd->pitches[0]; 240 fb->base.offsets[0] = cmd->offsets[0]; 241 fb->base.width = cmd->width; 242 fb->base.height = cmd->height; 243 fb->base.pixel_format = cmd->pixel_format; 244 drm_fb_get_bpp_depth(cmd->pixel_format, &fb->base.depth, 245 &fb->base.bits_per_pixel); 246 247 error = tegra_drm_framebuffer_init(ddev, fb); 248 if (error) 249 goto dealloc; 250 251 return &fb->base; 252 253 drm_framebuffer_cleanup(&fb->base); 254 dealloc: 255 kmem_free(fb, sizeof(*fb)); 256 unref: 257 drm_gem_object_unreference_unlocked(gem_obj); 258 259 return NULL; 260 } 261 262 static int 263 tegra_framebuffer_create_handle(struct drm_framebuffer *fb, 264 struct drm_file *file, unsigned int *handle) 265 { 266 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 267 268 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle); 269 } 270 271 static void 272 tegra_framebuffer_destroy(struct drm_framebuffer *fb) 273 { 274 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 275 276 drm_framebuffer_cleanup(fb); 277 drm_gem_object_unreference_unlocked(&tegra_fb->obj->base); 278 kmem_free(tegra_fb, sizeof(*tegra_fb)); 279 } 280 281 static int 282 tegra_crtc_init(struct drm_device *ddev, int index) 283 { 284 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 285 struct tegra_crtc *crtc; 286 bus_addr_t offset; 287 bus_size_t size; 288 u_int intr; 289 int error; 290 291 switch (index) { 292 case 0: 293 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET; 294 size = TEGRA_DISPLAYA_SIZE; 295 intr = TEGRA_INTR_DISPLAYA; 296 break; 297 case 1: 298 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET; 299 size = TEGRA_DISPLAYB_SIZE; 300 intr = TEGRA_INTR_DISPLAYB; 301 break; 302 default: 303 return -EINVAL; 304 } 305 306 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP); 307 if (crtc == NULL) 308 return -ENOMEM; 309 310 crtc->index = index; 311 crtc->bst = sc->sc_bst; 312 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh); 313 if (error) { 314 kmem_free(crtc, sizeof(*crtc)); 315 return -error; 316 } 317 crtc->size = size; 318 crtc->intr = intr; 319 crtc->ih = intr_establish(intr, IPL_VM, IST_LEVEL | IST_MPSAFE, 320 tegra_crtc_intr, crtc); 321 if (crtc->ih == NULL) { 322 DRM_ERROR("failed to establish interrupt for crtc %d\n", index); 323 } 324 const size_t cursor_size = 256 * 256 * 4; 325 crtc->cursor_obj = tegra_drm_obj_alloc(ddev, cursor_size); 326 if (crtc->cursor_obj == NULL) { 327 kmem_free(crtc, sizeof(*crtc)); 328 return -ENOMEM; 329 } 330 331 tegra_car_dc_enable(crtc->index); 332 333 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK); 334 335 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs); 336 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs); 337 338 return 0; 339 } 340 341 static int 342 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 343 uint32_t handle, uint32_t width, uint32_t height) 344 { 345 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 346 struct drm_gem_object *gem_obj = NULL; 347 struct tegra_gem_object *obj; 348 uint32_t cfg, opt; 349 int error; 350 351 if (tegra_crtc->enabled == false) 352 return 0; 353 354 if (handle == 0) { 355 /* hide cursor */ 356 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 357 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) { 358 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 359 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 360 /* Commit settings */ 361 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 362 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 363 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 364 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 365 } 366 error = 0; 367 goto done; 368 } 369 370 if ((width != height) || 371 (width != 32 && width != 64 && width != 128 && width != 256)) { 372 DRM_ERROR("Cursor dimension %ux%u not supported\n", 373 width, height); 374 error = -EINVAL; 375 goto done; 376 } 377 378 gem_obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 379 if (gem_obj == NULL) { 380 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n", 381 handle, tegra_crtc->index); 382 error = -ENOENT; 383 goto done; 384 } 385 obj = to_tegra_gem_obj(gem_obj); 386 387 if (obj->base.size < width * height * 4) { 388 DRM_ERROR("Cursor buffer is too small\n"); 389 error = -ENOMEM; 390 goto done; 391 } 392 393 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY, 394 DC_DISP_CURSOR_START_ADDR_CLIPPING); 395 switch (width) { 396 case 32: 397 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32, 398 DC_DISP_CURSOR_START_ADDR_SIZE); 399 break; 400 case 64: 401 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64, 402 DC_DISP_CURSOR_START_ADDR_SIZE); 403 break; 404 case 128: 405 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128, 406 DC_DISP_CURSOR_START_ADDR_SIZE); 407 break; 408 case 256: 409 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256, 410 DC_DISP_CURSOR_START_ADDR_SIZE); 411 break; 412 } 413 414 /* copy cursor (argb -> rgba) */ 415 struct tegra_gem_object *cursor_obj = tegra_crtc->cursor_obj; 416 uint32_t off, *cp = obj->dmap, *crtc_cp = cursor_obj->dmap; 417 for (off = 0; off < width * height; off++) { 418 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24); 419 } 420 421 cfg |= __SHIFTIN((cursor_obj->dmasegs[0].ds_addr >> 10) & 0x3fffff, 422 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO); 423 const uint32_t ocfg = 424 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG); 425 if (cfg != ocfg) { 426 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg); 427 } 428 429 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG); 430 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL; 431 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL); 432 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL; 433 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL); 434 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA; 435 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA); 436 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL; 437 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg); 438 439 /* set cursor position */ 440 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 441 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) | 442 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V)); 443 444 /* Commit settings */ 445 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 446 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 447 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 448 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 449 450 /* show cursor */ 451 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 452 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) { 453 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 454 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 455 456 /* Commit settings */ 457 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 458 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 459 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 460 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 461 } 462 463 error = 0; 464 465 done: 466 if (error == 0) { 467 /* Wait for activation request to complete */ 468 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) & 469 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ) 470 ; 471 } 472 473 if (gem_obj) { 474 drm_gem_object_unreference_unlocked(gem_obj); 475 } 476 477 return error; 478 } 479 480 static int 481 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 482 { 483 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 484 485 tegra_crtc->cursor_x = x & 0x3fff; 486 tegra_crtc->cursor_y = y & 0x3fff; 487 488 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 489 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) | 490 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V)); 491 492 /* Commit settings */ 493 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 494 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 495 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 496 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 497 498 return 0; 499 } 500 501 static void 502 tegra_crtc_destroy(struct drm_crtc *crtc) 503 { 504 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 505 drm_crtc_cleanup(crtc); 506 if (tegra_crtc->ih) { 507 intr_disestablish(tegra_crtc->ih); 508 } 509 tegra_drm_obj_free(tegra_crtc->cursor_obj); 510 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size); 511 kmem_free(tegra_crtc, sizeof(*tegra_crtc)); 512 } 513 514 static void 515 tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 516 { 517 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 518 519 switch (mode) { 520 case DRM_MODE_DPMS_ON: 521 case DRM_MODE_DPMS_STANDBY: 522 case DRM_MODE_DPMS_SUSPEND: 523 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 524 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0); 525 break; 526 case DRM_MODE_DPMS_OFF: 527 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 528 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 529 break; 530 } 531 } 532 533 static bool 534 tegra_crtc_mode_fixup(struct drm_crtc *crtc, 535 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 536 { 537 return true; 538 } 539 540 static int 541 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 542 struct drm_display_mode *adjusted_mode, int x, int y, 543 struct drm_framebuffer *old_fb) 544 { 545 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 546 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 547 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end; 548 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; 549 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 550 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 551 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay; 552 553 /* Set colour depth to ARGB8888 */ 554 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG, 555 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8, 556 DC_WINC_A_COLOR_DEPTH_DEPTH)); 557 558 /* Disable byte swapping */ 559 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG, 560 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP, 561 DC_WINC_A_BYTE_SWAP_SWAP)); 562 563 /* Initial DDA */ 564 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0); 565 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0); 566 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000); 567 568 /* Window position, size, stride */ 569 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG, 570 __SHIFTIN(0, DC_WINC_A_POSITION_V) | 571 __SHIFTIN(0, DC_WINC_A_POSITION_H)); 572 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG, 573 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) | 574 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H)); 575 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG, 576 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) | 577 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 578 DC_WINC_A_PRESCALED_SIZE_H)); 579 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG, 580 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 581 DC_WINC_A_LINE_STRIDE_LINE_STRIDE)); 582 583 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 584 585 /* Enable window A */ 586 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 587 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 588 589 /* Timing and signal options */ 590 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG, 591 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS)); 592 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG, 593 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888, 594 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE)); 595 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG, 596 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE); 597 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG, 598 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE, 599 DC_DISP_H_PULSE2_CONTROL_V_QUAL) | 600 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A, 601 DC_DISP_H_PULSE2_CONTROL_LAST)); 602 603 const u_int pulse_start = 1 + hspw + hbp - 10; 604 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG, 605 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) | 606 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END)); 607 608 /* Pixel clock */ 609 const u_int div = (tegra_car_plld2_rate() * 2) / 610 (mode->crtc_clock * 1000) - 2; 611 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG, 612 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) | 613 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER)); 614 615 /* Mode timings */ 616 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG, 617 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) | 618 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H)); 619 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG, 620 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) | 621 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H)); 622 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG, 623 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) | 624 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H)); 625 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG, 626 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) | 627 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H)); 628 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG, 629 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) | 630 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H)); 631 632 return 0; 633 } 634 635 static int 636 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 637 int x, int y, int atomic) 638 { 639 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 640 struct tegra_framebuffer *tegra_fb = atomic ? 641 to_tegra_framebuffer(fb) : 642 to_tegra_framebuffer(crtc->primary->fb); 643 644 /* Framebuffer start address */ 645 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, 646 (uint32_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr); 647 648 /* Offsets */ 649 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x); 650 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y); 651 652 /* Surface kind */ 653 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG, 654 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH, 655 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND)); 656 657 return 0; 658 } 659 660 static int 661 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 662 struct drm_framebuffer *old_fb) 663 { 664 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 665 666 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 667 668 /* Commit settings */ 669 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 670 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 671 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 672 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 673 674 return 0; 675 } 676 677 static int 678 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 679 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) 680 { 681 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 682 683 tegra_crtc_do_set_base(crtc, fb, x, y, 1); 684 685 /* Commit settings */ 686 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 687 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 688 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 689 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 690 691 return 0; 692 } 693 694 static void 695 tegra_crtc_disable(struct drm_crtc *crtc) 696 { 697 } 698 699 static void 700 tegra_crtc_prepare(struct drm_crtc *crtc) 701 { 702 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 703 704 /* Access control */ 705 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0); 706 707 /* Enable window A programming */ 708 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG, 709 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT); 710 } 711 712 static void 713 tegra_crtc_commit(struct drm_crtc *crtc) 714 { 715 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 716 717 /* Enable continuous display mode */ 718 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG, 719 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY, 720 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE)); 721 722 /* Enable power */ 723 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG, 724 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE | 725 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE | 726 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE | 727 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE | 728 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE | 729 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE | 730 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE, 731 0); 732 733 /* Commit settings */ 734 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 735 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 736 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 737 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 738 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 739 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 740 741 tegra_crtc->enabled = true; 742 } 743 744 static int 745 tegra_encoder_init(struct drm_device *ddev) 746 { 747 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 748 struct tegra_encoder *encoder; 749 int error; 750 751 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP); 752 if (encoder == NULL) 753 return -ENOMEM; 754 755 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET; 756 const bus_size_t size = TEGRA_HDMI_SIZE; 757 758 encoder->bst = sc->sc_bst; 759 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh); 760 if (error) { 761 kmem_free(encoder, sizeof(*encoder)); 762 return -error; 763 } 764 encoder->size = size; 765 766 tegra_pmc_hdmi_enable(); 767 768 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs, 769 DRM_MODE_ENCODER_TMDS); 770 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs); 771 772 encoder->base.possible_crtcs = (1 << 0) | (1 << 1); 773 774 return tegra_connector_init(ddev, &encoder->base); 775 } 776 777 static void 778 tegra_encoder_destroy(struct drm_encoder *encoder) 779 { 780 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 781 drm_encoder_cleanup(encoder); 782 kmem_free(tegra_encoder, sizeof(*tegra_encoder)); 783 } 784 785 static void 786 tegra_encoder_dpms(struct drm_encoder *encoder, int mode) 787 { 788 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 789 790 if (encoder->crtc == NULL) 791 return; 792 793 switch (mode) { 794 case DRM_MODE_DPMS_ON: 795 case DRM_MODE_DPMS_STANDBY: 796 case DRM_MODE_DPMS_SUSPEND: 797 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 798 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE); 799 break; 800 case DRM_MODE_DPMS_OFF: 801 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 802 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0); 803 break; 804 } 805 } 806 807 static bool 808 tegra_encoder_mode_fixup(struct drm_encoder *encoder, 809 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 810 { 811 return true; 812 } 813 814 static void 815 tegra_encoder_mode_set(struct drm_encoder *encoder, 816 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 817 { 818 struct drm_device *ddev = encoder->dev; 819 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 820 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc); 821 struct tegra_connector *tegra_connector = NULL; 822 struct drm_connector *connector; 823 const struct tegra_hdmi_tmds_config *tmds = NULL; 824 uint32_t input_ctrl; 825 int retry; 826 u_int i; 827 828 tegra_car_hdmi_enable(mode->crtc_clock * 1000); 829 830 /* find the connector for this encoder */ 831 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 832 if (connector->encoder == encoder) { 833 tegra_connector = to_tegra_connector(connector); 834 break; 835 } 836 } 837 838 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) { 839 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) { 840 break; 841 } 842 } 843 if (i < __arraycount(tegra_hdmi_tmds_config)) { 844 tmds = &tegra_hdmi_tmds_config[i]; 845 } else { 846 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 847 } 848 849 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 850 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 851 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 852 tmds->sor_lane_drive_current); 853 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG, 854 tmds->pe_current); 855 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 856 tmds->sor_io_peak_current); 857 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 858 tmds->sor_pad_ctls0); 859 860 const u_int div = (mode->crtc_clock / 1000) * 4; 861 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG, 862 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 863 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 864 865 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG, 866 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 867 HDMI_NV_PDISP_SOR_CSTM_MODE) | 868 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 869 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 870 HDMI_NV_PDISP_SOR_CSTM_MODE | 871 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 872 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 873 874 const uint32_t inst = 875 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 876 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 877 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 878 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 879 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 880 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 881 882 input_ctrl = __SHIFTIN(tegra_crtc->index, 883 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 884 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480) 885 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 886 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 887 888 /* Start SOR */ 889 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 890 0, 891 HDMI_NV_PDISP_SOR_PLL0_PWR | 892 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 893 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 894 delay(10); 895 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 896 0, 897 HDMI_NV_PDISP_SOR_PLL0_PDBG); 898 899 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 900 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 901 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 902 903 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 904 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 905 906 for (retry = 10000; retry > 0; retry--) { 907 const uint32_t pwr = HDMI_READ(tegra_encoder, 908 HDMI_NV_PDISP_SOR_PWR_REG); 909 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 910 break; 911 delay(10); 912 } 913 if (retry == 0) { 914 DRM_ERROR("timeout enabling SOR power\n"); 915 } 916 917 uint32_t state2 = 918 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 919 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 920 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 921 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 922 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 923 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 924 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 925 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 926 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 927 928 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 929 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 930 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 931 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 932 933 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 934 935 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 936 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 937 938 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 939 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 940 941 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 942 943 const u_int rekey = 56; 944 const u_int hspw = mode->hsync_end - mode->hsync_start; 945 const u_int hbp = mode->htotal - mode->hsync_end; 946 const u_int hfp = mode->hsync_start - mode->hdisplay; 947 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 948 uint32_t ctrl = 949 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 950 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 951 if (tegra_connector && tegra_connector->has_hdmi_sink) { 952 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 953 } 954 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 955 956 if (tegra_connector && tegra_connector->has_hdmi_sink && 957 tegra_connector->has_audio) { 958 struct hdmi_audio_infoframe ai; 959 struct hdmi_avi_infoframe avii; 960 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 961 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 962 const u_int n = 6144; /* 48 kHz */ 963 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480; 964 965 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG, 966 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO, 967 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) | 968 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL); 969 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 970 HDMI_NV_PDISP_AUDIO_N_RESETF | 971 HDMI_NV_PDISP_AUDIO_N_GENERATE | 972 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE)); 973 974 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG, 975 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS | 976 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS | 977 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL)); 978 979 /* 980 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by 981 * software in the 44.1 kHz register regardless of chosen rate. 982 */ 983 HDMI_WRITE(tegra_encoder, 984 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG, 985 cts << 8); 986 HDMI_WRITE(tegra_encoder, 987 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG, 988 0x80000000 | n); 989 990 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0, 991 HDMI_NV_PDISP_AUDIO_N_RESETF); 992 993 HDMI_WRITE(tegra_encoder, 994 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000); 995 996 hdmi_audio_infoframe_init(&ai); 997 ai.channels = 2; 998 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf)); 999 HDMI_WRITE(tegra_encoder, 1000 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG, 1001 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16)); 1002 HDMI_WRITE(tegra_encoder, 1003 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG, 1004 aibuf[3] | (aibuf[4] << 8) | 1005 (aibuf[5] << 16) | (aibuf[6] << 24)); 1006 HDMI_WRITE(tegra_encoder, 1007 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG, 1008 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16)); 1009 1010 hdmi_avi_infoframe_init(&avii); 1011 drm_hdmi_avi_infoframe_from_display_mode(&avii, mode); 1012 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf)); 1013 HDMI_WRITE(tegra_encoder, 1014 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG, 1015 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16)); 1016 HDMI_WRITE(tegra_encoder, 1017 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG, 1018 aviibuf[3] | (aviibuf[4] << 8) | 1019 (aviibuf[5] << 16) | (aviibuf[6] << 24)); 1020 HDMI_WRITE(tegra_encoder, 1021 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG, 1022 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16)); 1023 HDMI_WRITE(tegra_encoder, 1024 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG, 1025 aviibuf[10] | (aviibuf[11] << 8) | 1026 (aviibuf[12] << 16) | (aviibuf[13] << 24)); 1027 HDMI_WRITE(tegra_encoder, 1028 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG, 1029 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16)); 1030 1031 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 1032 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO); 1033 HDMI_WRITE(tegra_encoder, 1034 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 1035 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE); 1036 HDMI_WRITE(tegra_encoder, 1037 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 1038 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE); 1039 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1040 } else { 1041 HDMI_WRITE(tegra_encoder, 1042 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 1043 HDMI_WRITE(tegra_encoder, 1044 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 1045 HDMI_WRITE(tegra_encoder, 1046 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 1047 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1048 } 1049 1050 /* Enable DC output to HDMI */ 1051 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, 1052 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0); 1053 1054 /* Commit settings */ 1055 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1056 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 1057 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 1058 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1059 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 1060 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 1061 } 1062 1063 static void 1064 tegra_encoder_prepare(struct drm_encoder *encoder) 1065 { 1066 } 1067 1068 static void 1069 tegra_encoder_commit(struct drm_encoder *encoder) 1070 { 1071 } 1072 1073 static int 1074 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder) 1075 { 1076 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1077 struct tegra_connector *connector; 1078 1079 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP); 1080 if (connector == NULL) 1081 return -ENOMEM; 1082 1083 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs, 1084 DRM_MODE_CONNECTOR_HDMIA); 1085 drm_connector_helper_add(&connector->base, 1086 &tegra_connector_helper_funcs); 1087 1088 connector->base.interlace_allowed = 0; 1089 connector->base.doublescan_allowed = 0; 1090 1091 drm_sysfs_connector_add(&connector->base); 1092 1093 connector->base.polled = 1094 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1095 1096 drm_mode_connector_attach_encoder(&connector->base, encoder); 1097 1098 connector->hpd = sc->sc_pin_hpd; 1099 if (!connector->hpd) 1100 DRM_ERROR("failed to find hpd pin for connector\n"); 1101 1102 connector->ddc = sc->sc_ddc; 1103 if (!connector->ddc) 1104 DRM_ERROR("failed to find ddc device for connector\n"); 1105 1106 return 0; 1107 } 1108 1109 static void 1110 tegra_connector_destroy(struct drm_connector *connector) 1111 { 1112 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1113 1114 drm_sysfs_connector_remove(connector); 1115 drm_connector_cleanup(connector); 1116 kmem_free(tegra_connector, sizeof(*tegra_connector)); 1117 } 1118 1119 static enum drm_connector_status 1120 tegra_connector_detect(struct drm_connector *connector, bool force) 1121 { 1122 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1123 bool con; 1124 1125 1126 if (!tegra_connector->hpd) { 1127 tegra_connector->has_hdmi_sink = false; 1128 tegra_connector->has_audio = false; 1129 return connector_status_connected; 1130 } 1131 1132 con = fdtbus_gpio_read(tegra_connector->hpd); 1133 if (con) { 1134 return connector_status_connected; 1135 } else { 1136 prop_dictionary_t prop = device_properties(connector->dev->dev); 1137 prop_dictionary_remove(prop, "physical-address"); 1138 tegra_connector->has_hdmi_sink = false; 1139 tegra_connector->has_audio = false; 1140 return connector_status_disconnected; 1141 } 1142 } 1143 1144 static int 1145 tegra_connector_mode_valid(struct drm_connector *connector, 1146 struct drm_display_mode *mode) 1147 { 1148 return MODE_OK; 1149 } 1150 1151 static int 1152 tegra_connector_get_modes(struct drm_connector *connector) 1153 { 1154 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1155 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev); 1156 prop_dictionary_t prop = device_properties(connector->dev->dev); 1157 char edid[EDID_LENGTH * 4]; 1158 struct edid *pedid = NULL; 1159 int error, block; 1160 1161 if (tegra_connector->ddc) { 1162 memset(edid, 0, sizeof(edid)); 1163 for (block = 0; block < 4; block++) { 1164 error = ddc_read_edid_block(tegra_connector->ddc, 1165 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 1166 if (error) 1167 break; 1168 if (block == 0) { 1169 pedid = (struct edid *)edid; 1170 if (edid[0x7e] == 0) 1171 break; 1172 } 1173 } 1174 } 1175 1176 if (pedid) { 1177 if (sc->sc_force_dvi) { 1178 tegra_connector->has_hdmi_sink = false; 1179 tegra_connector->has_audio = false; 1180 } else { 1181 tegra_connector->has_hdmi_sink = 1182 drm_detect_hdmi_monitor(pedid); 1183 tegra_connector->has_audio = 1184 drm_detect_monitor_audio(pedid); 1185 } 1186 drm_mode_connector_update_edid_property(connector, pedid); 1187 error = drm_add_edid_modes(connector, pedid); 1188 drm_edid_to_eld(connector, pedid); 1189 if (drm_detect_hdmi_monitor(pedid)) { 1190 prop_dictionary_set_uint16(prop, "physical-address", 1191 connector->physical_address); 1192 } 1193 return error; 1194 } else { 1195 drm_mode_connector_update_edid_property(connector, NULL); 1196 return 0; 1197 } 1198 } 1199 1200 static struct drm_encoder * 1201 tegra_connector_best_encoder(struct drm_connector *connector) 1202 { 1203 int enc_id = connector->encoder_ids[0]; 1204 struct drm_mode_object *obj; 1205 struct drm_encoder *encoder = NULL; 1206 1207 if (enc_id) { 1208 obj = drm_mode_object_find(connector->dev, enc_id, 1209 DRM_MODE_OBJECT_ENCODER); 1210 if (obj == NULL) 1211 return NULL; 1212 encoder = obj_to_encoder(obj); 1213 } 1214 1215 return encoder; 1216 } 1217 1218 static int 1219 tegra_crtc_intr(void *priv) 1220 { 1221 struct tegra_crtc *tegra_crtc = priv; 1222 struct drm_device *ddev = tegra_crtc->base.dev; 1223 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1224 int rv = 0; 1225 1226 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG); 1227 1228 if (status & DC_CMD_INT_V_BLANK) { 1229 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1230 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]); 1231 drm_handle_vblank(ddev, tegra_crtc->index); 1232 rv = 1; 1233 } 1234 1235 return rv; 1236 } 1237 1238 u32 1239 tegra_drm_get_vblank_counter(struct drm_device *ddev, int crtc) 1240 { 1241 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1242 1243 if (crtc > 1) 1244 return 0; 1245 1246 return sc->sc_vbl_received[crtc]; 1247 } 1248 1249 int 1250 tegra_drm_enable_vblank(struct drm_device *ddev, int crtc) 1251 { 1252 struct tegra_crtc *tegra_crtc = NULL; 1253 struct drm_crtc *iter; 1254 1255 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1256 if (to_tegra_crtc(iter)->index == crtc) { 1257 tegra_crtc = to_tegra_crtc(iter); 1258 break; 1259 } 1260 } 1261 if (tegra_crtc == NULL) 1262 return -EINVAL; 1263 1264 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0); 1265 1266 return 0; 1267 } 1268 1269 void 1270 tegra_drm_disable_vblank(struct drm_device *ddev, int crtc) 1271 { 1272 struct tegra_crtc *tegra_crtc = NULL; 1273 struct drm_crtc *iter; 1274 1275 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1276 if (to_tegra_crtc(iter)->index == crtc) { 1277 tegra_crtc = to_tegra_crtc(iter); 1278 break; 1279 } 1280 } 1281 if (tegra_crtc == NULL) 1282 return; 1283 1284 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK); 1285 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1286 } 1287