1 /* $NetBSD: tegra_dcreg.h,v 1.5 2015/11/14 11:55:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_DCREG_H 30 #define _ARM_TEGRA_DCREG_H 31 32 /* 33 * Display CMD registers 34 */ 35 #define DC_CMD_GENERAL_INCR_SYNCPT_REG 0x000 36 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_REG 0x004 37 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_REG 0x008 38 #define DC_CMD_WIN_A_INCR_SYNCPT_REG 0x020 39 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_REG 0x024 40 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_REG 0x028 41 #define DC_CMD_WIN_B_INCR_SYNCPT_REG 0x040 42 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_REG 0x044 43 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_REG 0x048 44 #define DC_CMD_WIN_C_INCR_SYNCPT_REG 0x060 45 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_REG 0x064 46 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_REG 0x068 47 #define DC_CMD_CONT_SYNCPT_VSYNC_REG 0x0a0 48 #define DC_CMD_CTXSW_REG 0x0c0 49 #define DC_CMD_DISPLAY_COMMAND_OPTION0_REG 0x0c4 50 51 #define DC_CMD_DISPLAY_COMMAND_REG 0x0c8 52 #define DC_CMD_DISPLAY_COMMAND_RAISE_CHANNEL_ID __BITS(30,27) 53 #define DC_CMD_DISPLAY_COMMAND_RAISE_VECTOR __BITS(26,22) 54 #define DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE __BITS(6,5) 55 #define DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_STOP 0 56 #define DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY 1 57 #define DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_NC_DISPLAY 2 58 #define DC_CMD_DISPLAY_COMMAND_RAISE __BIT(0) 59 60 #define DC_CMD_SIGNAL_RAISE_REG 0x0cc 61 62 #define DC_CMD_DISPLAY_POWER_CONTROL_REG 0x0d8 63 #define DC_CMD_DISPLAY_POWER_CONTROL_HSPI_ENABLE __BIT(25) 64 #define DC_CMD_DISPLAY_POWER_CONTROL_SPI_ENABLE __BIT(24) 65 #define DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE __BIT(18) 66 #define DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE __BIT(16) 67 #define DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE __BIT(8) 68 #define DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE __BIT(6) 69 #define DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE __BIT(4) 70 #define DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE __BIT(2) 71 #define DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE __BIT(0) 72 73 #define DC_CMD_INT_STATUS_REG 0x0dc 74 #define DC_CMD_INT_MASK_REG 0x0e0 75 #define DC_CMD_INT_ENABLE_REG 0x0e4 76 #define DC_CMD_INT_V_BLANK __BIT(2) 77 78 #define DC_CMD_INT_TYPE_REG 0x0e8 79 #define DC_CMD_INT_POLARITY_REG 0x0ec 80 #define DC_CMD_SIGNAL_RAISE1_REG 0x0f0 81 #define DC_CMD_SIGNAL_RAISE2_REG 0x0f4 82 #define DC_CMD_SIGNAL_RAISE3_REG 0x0f8 83 84 #define DC_CMD_STATE_ACCESS_REG 0x100 85 #define DC_CMD_STATE_ACCESS_WRITE_MUX __BIT(2) 86 #define DC_CMD_STATE_ACCESS_READ_MUX __BIT(0) 87 88 #define DC_CMD_STATE_CONTROL_REG 0x104 89 #define DC_CMD_STATE_CONTROL_NC_HOST_TRIG_ENABLE __BIT(24) 90 #define DC_CMD_STATE_CONTROL_CURSOR_UPDATE __BIT(15) 91 #define DC_CMD_STATE_CONTROL_WIN_D_UPDATE __BIT(12) 92 #define DC_CMD_STATE_CONTROL_WIN_C_UPDATE __BIT(11) 93 #define DC_CMD_STATE_CONTROL_WIN_B_UPDATE __BIT(10) 94 #define DC_CMD_STATE_CONTROL_WIN_A_UPDATE __BIT(9) 95 #define DC_CMD_STATE_CONTROL_GENERAL_UPDATE __BIT(8) 96 #define DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ __BIT(7) 97 #define DC_CMD_STATE_CONTROL_WIN_D_ACT_REQ __BIT(4) 98 #define DC_CMD_STATE_CONTROL_WIN_C_ACT_REQ __BIT(3) 99 #define DC_CMD_STATE_CONTROL_WIN_B_ACT_REQ __BIT(2) 100 #define DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ __BIT(1) 101 #define DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ __BIT(0) 102 103 #define DC_CMD_DISPLAY_WINDOW_HEADER_REG 0x108 104 #define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_D_SELECT __BIT(7) 105 #define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_C_SELECT __BIT(6) 106 #define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_B_SELECT __BIT(5) 107 #define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT __BIT(4) 108 109 #define DC_CMD_REG_ACT_CONTROL_REG 0x10c 110 #define DC_CMD_WIN_T_STATE_CONTROL_REG 0x110 111 #define DC_CMD_SECURE_CONTROL_REG 0x114 112 #define DC_CMD_WIN_D_INCR_SYNCPT_REG 0x130 113 #define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_REG 0x134 114 #define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_REG 0x138 115 116 /* 117 * Display COM registers 118 */ 119 #define DC_COM_CRC_CONTROL_REG 0xc00 120 #define DC_COM_CRC_CHECKSUM_REG 0xc04 121 #define DC_COM_PIN_MISC_CONTROL_REG 0xc6c 122 #define DC_COM_PM0_CONTROL_REG 0xc70 123 #define DC_COM_PM0_DUTY_CYCLE_REG 0xc74 124 #define DC_COM_SCRATCH_REGISTER_A_REG 0xc94 125 #define DC_COM_SCRATCH_REGISTER_B_REG 0xc98 126 #define DC_COM_CRC_CHECKSUM_LATCHED_REG 0xca4 127 #define DC_COM_CMU_CSC_KRR_REG 0xca8 128 #define DC_COM_CMU_CSC_KGR_REG 0xcac 129 #define DC_COM_CMU_CSC_KBR_REG 0xcb0 130 #define DC_COM_CMU_CSC_KRG_REG 0xcb4 131 #define DC_COM_CMU_CSC_KGG_REG 0xcb8 132 #define DC_COM_CMU_CSC_KBG_REG 0xcbc 133 #define DC_COM_CMU_CSC_KRB_REG 0xcc0 134 #define DC_COM_CMU_CSC_KGB_REG 0xcc4 135 #define DC_COM_CMU_CSC_KBB_REG 0xcc8 136 #define DC_COM_CMU_LUT_MASK_REG 0xccc 137 #define DC_COM_CMU_LUT1_REG 0xcd8 138 #define DC_COM_CMU_LUT2_REG 0xcdc 139 140 /* 141 * Display DISP registers 142 */ 143 #define DC_DISP_DISP_SIGNAL_OPTIONS0_REG 0x1000 144 #define DC_DISP_DISP_SIGNAL_OPTIONS0_M1_ENABLE __BIT(26) 145 #define DC_DISP_DISP_SIGNAL_OPTIONS0_M0_ENABLE __BIT(24) 146 #define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE3_ENABLE __BIT(20) 147 #define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE2_ENABLE __BIT(19) 148 #define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE1_ENABLE __BIT(18) 149 #define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE0_ENABLE __BIT(16) 150 #define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE __BIT(12) 151 #define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE1_ENABLE __BIT(10) 152 #define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE0_ENABLE __BIT(8) 153 154 #define DC_DISP_DISP_WIN_OPTIONS_REG 0x1008 155 #define DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE __BIT(30) 156 #define DC_DISP_DISP_WIN_OPTIONS_DSI_ENABLE __BIT(29) 157 #define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE __BIT(25) 158 #define DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE __BIT(16) 159 160 #define DC_DISP_DISP_TIMING_OPTIONS_REG 0x1014 161 #define DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS __BITS(11,0) 162 163 #define DC_DISP_REF_TO_SYNC_REG 0x1018 164 #define DC_DISP_REF_TO_SYNC_V __BITS(28,16) 165 #define DC_DISP_REF_TO_SYNC_H __BITS(12,0) 166 167 #define DC_DISP_SYNC_WIDTH_REG 0x101c 168 #define DC_DISP_SYNC_WIDTH_V __BITS(28,16) 169 #define DC_DISP_SYNC_WIDTH_H __BITS(12,0) 170 171 #define DC_DISP_BACK_PORCH_REG 0x1020 172 #define DC_DISP_BACK_PORCH_V __BITS(28,16) 173 #define DC_DISP_BACK_PORCH_H __BITS(12,0) 174 175 #define DC_DISP_DISP_ACTIVE_REG 0x1024 176 #define DC_DISP_DISP_ACTIVE_V __BITS(28,16) 177 #define DC_DISP_DISP_ACTIVE_H __BITS(12,0) 178 179 #define DC_DISP_FRONT_PORCH_REG 0x1028 180 #define DC_DISP_FRONT_PORCH_V __BITS(28,16) 181 #define DC_DISP_FRONT_PORCH_H __BITS(12,0) 182 183 #define DC_DISP_H_PULSE0_CONTROL_REG 0x102c 184 #define DC_DISP_H_PULSE0_POSITION_A_REG 0x1030 185 #define DC_DISP_H_PULSE0_POSITION_B_REG 0x1034 186 #define DC_DISP_H_PULSE0_POSITION_C_REG 0x1038 187 #define DC_DISP_H_PULSE0_POSITION_D_REG 0x103c 188 #define DC_DISP_H_PULSE1_CONTROL_REG 0x1040 189 #define DC_DISP_H_PULSE1_POSITION_A_REG 0x1044 190 #define DC_DISP_H_PULSE1_POSITION_B_REG 0x1048 191 #define DC_DISP_H_PULSE1_POSITION_C_REG 0x104c 192 #define DC_DISP_H_PULSE1_POSITION_D_REG 0x1050 193 194 #define DC_DISP_H_PULSE2_CONTROL_REG 0x1054 195 #define DC_DISP_H_PULSE2_CONTROL_LAST __BITS(11,8) 196 #define DC_DISP_H_PULSE2_CONTROL_LAST_END_A 1 197 #define DC_DISP_H_PULSE2_CONTROL_V_QUAL __BITS(7,6) 198 #define DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE 2 199 #define DC_DISP_H_PULSE2_CONTROL_POLARITY __BIT(4) 200 #define DC_DISP_H_PULSE2_CONTROL_MODE __BIT(3) 201 202 #define DC_DISP_H_PULSE2_POSITION_A_REG 0x1058 203 #define DC_DISP_H_PULSE2_POSITION_A_END __BITS(28,16) 204 #define DC_DISP_H_PULSE2_POSITION_A_START __BITS(12,0) 205 206 #define DC_DISP_H_PULSE2_POSITION_B_REG 0x105c 207 #define DC_DISP_H_PULSE2_POSITION_C_REG 0x1060 208 #define DC_DISP_H_PULSE2_POSITION_D_REG 0x1064 209 #define DC_DISP_V_PULSE0_CONTROL_REG 0x1068 210 #define DC_DISP_V_PULSE0_POSITION_A_REG 0x106c 211 #define DC_DISP_V_PULSE0_POSITION_B_REG 0x1070 212 #define DC_DISP_V_PULSE0_POSITION_C_REG 0x1074 213 #define DC_DISP_V_PULSE1_CONTROL_REG 0x1078 214 #define DC_DISP_V_PULSE1_POSITION_A_REG 0x107c 215 #define DC_DISP_V_PULSE1_POSITION_B_REG 0x1080 216 #define DC_DISP_V_PULSE1_POSITION_C_REG 0x1084 217 #define DC_DISP_V_PULSE2_CONTROL_REG 0x1088 218 #define DC_DISP_V_PULSE2_POSITION_A_REG 0x108c 219 #define DC_DISP_V_PULSE3_CONTROL_REG 0x1090 220 #define DC_DISP_V_PULSE3_POSITION_A_REG 0x1094 221 222 #define DC_DISP_DISP_CLOCK_CONTROL_REG 0x10b8 223 #define DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER __BITS(11,8) 224 #define DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER __BITS(7,0) 225 226 #define DC_DISP_DISP_INTERFACE_CONTROL_REG 0x10bc 227 228 #define DC_DISP_DISP_COLOR_CONTROL_REG 0x10c0 229 #define DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE __BITS(3,0) 230 #define DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888 8 231 232 #define DC_DISP_COLOR_KEY0_LOWER_REG 0x10d8 233 #define DC_DISP_COLOR_KEY0_UPPER_REG 0x10dc 234 #define DC_DISP_COLOR_KEY1_LOWER_REG 0x10e0 235 #define DC_DISP_COLOR_KEY1_UPPER_REG 0x10e4 236 #define DC_DISP_CURSOR_FOREGROUND_REG 0x10f0 237 #define DC_DISP_CURSOR_BACKGROUND_REG 0x10f4 238 239 #define DC_DISP_CURSOR_START_ADDR_REG 0x10f8 240 #define DC_DISP_CURSOR_START_ADDR_CLIPPING __BITS(29,28) 241 #define DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY 0 242 #define DC_DISP_CURSOR_START_ADDR_CLIPPING_WA 1 243 #define DC_DISP_CURSOR_START_ADDR_CLIPPING_WB 2 244 #define DC_DISP_CURSOR_START_ADDR_CLIPPING_WC 3 245 #define DC_DISP_CURSOR_START_ADDR_SIZE __BITS(25,24) 246 #define DC_DISP_CURSOR_START_ADDR_SIZE_32 0 247 #define DC_DISP_CURSOR_START_ADDR_SIZE_64 1 248 #define DC_DISP_CURSOR_START_ADDR_SIZE_128 2 249 #define DC_DISP_CURSOR_START_ADDR_SIZE_256 3 250 #define DC_DISP_CURSOR_START_ADDR_ADDRESS_LO __BITS(21,0) 251 252 #define DC_DISP_CURSOR_START_ADDR_NS_REG 0x10fc 253 254 #define DC_DISP_CURSOR_POSITION_REG 0x1100 255 #define DC_DISP_CURSOR_POSITION_V __BITS(29,16) 256 #define DC_DISP_CURSOR_POSITION_H __BITS(13,0) 257 258 #define DC_DISP_CURSOR_POSITION_NS_REG 0x1104 259 #define DC_DISP_DC_MCCIF_FIFOCTRL_REG 0x1200 260 #define DC_DISP_MCCIF_DISPLAY0A_HYST_REG 0x1204 261 #define DC_DISP_MCCIF_DISPLAY0B_HYST_REG 0x1208 262 #define DC_DISP_MCCIF_DISPLAY0C_HYST_REG 0x120c 263 #define DC_DISP_DISP_MISC_CONTROL_REG 0x1304 264 #define DC_DISP_SD_CONTROL_REG 0x1308 265 #define DC_DISP_SD_CSC_COEFF_REG 0x130c 266 #define DC_DISP_SD_LUT_REG 0x1310 267 #define DC_DISP_SD_FLICKER_CONTROL_REG 0x1334 268 #define DC_DISP_SD_PIXEL_COUNT_REG 0x1338 269 #define DC_DISP_SD_HISTOGRAM_REG 0x133c 270 #define DC_DISP_SD_BL_PARAMETERS_REG 0x135c 271 #define DC_DISP_SD_BL_TF_REG 0x1360 272 #define DC_DISP_SD_BL_CONTROL_REG 0x1370 273 #define DC_DISP_SD_HW_K_VALUES_REG 0x1374 274 #define DC_DISP_SD_MAN_K_VALUES_REG 0x1378 275 #define DC_DISP_SD_K_LIMIT_REG 0x137c 276 #define DC_DISP_SD_WINDOW_POSITION_REG 0x1380 277 #define DC_DISP_SD_WINDOW_SIZE_REG 0x1384 278 #define DC_DISP_SD_SOFT_CLIPPING_REG 0x1388 279 #define DC_DISP_SD_SMOOTH_K_REG 0x138c 280 #define DC_DISP_BLEND_BACKGROUND_COLOR_REG 0x1390 281 #define DC_DISP_INTERLACE_CONTROL_REG 0x1394 282 #define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_REG 0x1398 283 #define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_REG 0x139c 284 #define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_REG 0x13a0 285 #define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_REG 0x13a4 286 #define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_REG 0x13a8 287 #define DC_DISP_CURSOR_UNDERFLOW_CTRL_REG 0x13ac 288 #define DC_DISP_CURSOR_START_ADDR_HI_REG 0x13b0 289 #define DC_DISP_CURSOR_START_ADDR_HI_NS_REG 0x13b4 290 #define DC_DISP_CURSOR_INTERLACE_CONTROL_REG 0x13b8 291 #define DC_DISP_CSC2_CONTROL_REG 0x13bc 292 293 #define DC_DISP_BLEND_CURSOR_CONTROL_REG 0x13c4 294 #define DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL __BIT(24) 295 #define DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL __BITS(17,16) 296 #define DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL __BITS(9,8) 297 #define DC_DISP_BLEND_CURSOR_CONTROL_ALPHA __BITS(7,0) 298 299 #define DC_DISP_DVFS_CURSOR_CONTROL_REG 0x13c8 300 #define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_REG 0x13cc 301 #define DC_DISP_CURSOR_SPOOLUP_CONTROL_REG 0x13d0 302 #define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_REG 0x13d4 303 #define DC_DISP_DISPLAY_DBG_TIMING_REG 0x13d8 304 #define DC_DISP_DISPLAY_SPARE0_REG 0x13dc 305 #define DC_DISP_DISPLAY_SPARE1_REG 0x13e0 306 307 /* 308 * Window A registers 309 */ 310 #define DC_WINC_A_COLOR_PALETTE_REG 0x1400 311 #define DC_WINC_A_PALETTE_COLOR_EXT_REG 0x1800 312 #define DC_WINC_A_H_FILTER_P00_REG 0x1804 313 #define DC_WINC_A_H_FILTER_P01_REG 0x1808 314 #define DC_WINC_A_H_FILTER_P02_REG 0x180c 315 #define DC_WINC_A_H_FILTER_P03_REG 0x1810 316 #define DC_WINC_A_H_FILTER_P04_REG 0x1814 317 #define DC_WINC_A_H_FILTER_P05_REG 0x1818 318 #define DC_WINC_A_H_FILTER_P06_REG 0x181c 319 #define DC_WINC_A_H_FILTER_P07_REG 0x1820 320 #define DC_WINC_A_H_FILTER_P08_REG 0x1824 321 #define DC_WINC_A_H_FILTER_P09_REG 0x1828 322 #define DC_WINC_A_H_FILTER_P0A_REG 0x182c 323 #define DC_WINC_A_H_FILTER_P0B_REG 0x1830 324 #define DC_WINC_A_H_FILTER_P0C_REG 0x1834 325 #define DC_WINC_A_H_FILTER_P0D_REG 0x1838 326 #define DC_WINC_A_H_FILTER_P0E_REG 0x183c 327 #define DC_WINC_A_H_FILTER_P0F_REG 0x1840 328 #define DC_WINC_A_CSC_YOF_REG 0x1844 329 #define DC_WINC_A_CSC_KYRGB_REG 0x1848 330 #define DC_WINC_A_CSC_KUR_REG 0x184c 331 #define DC_WINC_A_CSC_KVR_REG 0x1850 332 #define DC_WINC_A_CSC_KUG_REG 0x1854 333 #define DC_WINC_A_CSC_KVG_REG 0x1858 334 #define DC_WINC_A_CSC_KUB_REG 0x185c 335 #define DC_WINC_A_CSC_KVB_REG 0x1860 336 #define DC_WINC_A_V_FILTER_P00_REG 0x1864 337 #define DC_WINC_A_V_FILTER_P01_REG 0x1868 338 #define DC_WINC_A_V_FILTER_P02_REG 0x186c 339 #define DC_WINC_A_V_FILTER_P03_REG 0x1870 340 #define DC_WINC_A_V_FILTER_P04_REG 0x1874 341 #define DC_WINC_A_V_FILTER_P05_REG 0x1878 342 #define DC_WINC_A_V_FILTER_P06_REG 0x187c 343 #define DC_WINC_A_V_FILTER_P07_REG 0x1880 344 #define DC_WINC_A_V_FILTER_P08_REG 0x1884 345 #define DC_WINC_A_V_FILTER_P09_REG 0x1888 346 #define DC_WINC_A_V_FILTER_P0A_REG 0x188c 347 #define DC_WINC_A_V_FILTER_P0B_REG 0x1890 348 #define DC_WINC_A_V_FILTER_P0C_REG 0x1894 349 #define DC_WINC_A_V_FILTER_P0D_REG 0x1898 350 #define DC_WINC_A_V_FILTER_P0E_REG 0x189c 351 #define DC_WINC_A_V_FILTER_P0F_REG 0x18a0 352 #define DC_WINC_A_H_FILTER_HI_P00_REG 0x18a4 353 #define DC_WINC_A_H_FILTER_HI_P01_REG 0x18a8 354 #define DC_WINC_A_H_FILTER_HI_P02_REG 0x18ac 355 #define DC_WINC_A_H_FILTER_HI_P03_REG 0x18b0 356 #define DC_WINC_A_H_FILTER_HI_P04_REG 0x18b4 357 #define DC_WINC_A_H_FILTER_HI_P05_REG 0x18b8 358 #define DC_WINC_A_H_FILTER_HI_P06_REG 0x18bc 359 #define DC_WINC_A_H_FILTER_HI_P07_REG 0x18c0 360 #define DC_WINC_A_H_FILTER_HI_P08_REG 0x18c4 361 #define DC_WINC_A_H_FILTER_HI_P09_REG 0x18c8 362 #define DC_WINC_A_H_FILTER_HI_P0A_REG 0x18cc 363 #define DC_WINC_A_H_FILTER_HI_P0B_REG 0x18d0 364 #define DC_WINC_A_H_FILTER_HI_P0C_REG 0x18d4 365 #define DC_WINC_A_H_FILTER_HI_P0D_REG 0x18d8 366 #define DC_WINC_A_H_FILTER_HI_P0E_REG 0x18dc 367 #define DC_WINC_A_H_FILTER_HI_P0F_REG 0x18e0 368 369 #define DC_WINC_A_WIN_OPTIONS_REG 0x1c00 370 #define DC_WINC_A_WIN_OPTIONS_H_FILTER_MODE __BIT(31) 371 #define DC_WINC_A_WIN_OPTIONS_WIN_ENABLE __BIT(30) 372 #define DC_WINC_A_WIN_OPTIONS_INTERLACE_ENABLE __BIT(23) 373 #define DC_WINC_A_WIN_OPTIONS_YUV_RANGE_EXPAND __BIT(22) 374 #define DC_WINC_A_WIN_OPTIONS_DV_ENABLE __BIT(20) 375 #define DC_WINC_A_WIN_OPTIONS_CSC_ENABLE __BIT(18) 376 #define DC_WINC_A_WIN_OPTIONS_CP_ENABLE __BIT(16) 377 #define DC_WINC_A_WIN_OPTIONS_V_FILTER_UV_ALIGN __BIT(14) 378 #define DC_WINC_A_WIN_OPTIONS_V_FILTER_OPTIMIZE __BIT(12) 379 #define DC_WINC_A_WIN_OPTIONS_V_FILTER_ENABLE __BIT(10) 380 #define DC_WINC_A_WIN_OPTIONS_H_FILTER_ENABLE __BIT(8) 381 #define DC_WINC_A_WIN_OPTIONS_COLOR_EXPAND __BIT(6) 382 #define DC_WINC_A_WIN_OPTIONS_SCAN_COLUMN __BIT(4) 383 #define DC_WINC_A_WIN_OPTIONS_V_DIRECTION __BIT(2) 384 #define DC_WINC_A_WIN_OPTIONS_H_DIRECTION __BIT(0) 385 386 #define DC_WINC_A_BYTE_SWAP_REG 0x1c04 387 #define DC_WINC_A_BYTE_SWAP_SWAP __BITS(2,0) 388 #define DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP 0 389 390 #define DC_WINC_A_COLOR_DEPTH_REG 0x1c0c 391 #define DC_WINC_A_COLOR_DEPTH_DEPTH __BITS(6,0) 392 #define DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8 12 393 #define DC_WINC_A_COLOR_DEPTH_DEPTH_T_X8R8G8B8 37 394 395 #define DC_WINC_A_POSITION_REG 0x1c10 396 #define DC_WINC_A_POSITION_V __BITS(28,16) 397 #define DC_WINC_A_POSITION_H __BITS(12,0) 398 399 #define DC_WINC_A_SIZE_REG 0x1c14 400 #define DC_WINC_A_SIZE_V __BITS(28,16) 401 #define DC_WINC_A_SIZE_H __BITS(12,0) 402 403 #define DC_WINC_A_PRESCALED_SIZE_REG 0x1c18 404 #define DC_WINC_A_PRESCALED_SIZE_V __BITS(28,16) 405 #define DC_WINC_A_PRESCALED_SIZE_H __BITS(14,0) 406 407 #define DC_WINC_A_H_INITIAL_DDA_REG 0x1c1c 408 #define DC_WINC_A_V_INITIAL_DDA_REG 0x1c20 409 #define DC_WINC_A_DDA_INCREMENT_REG 0x1c24 410 411 #define DC_WINC_A_LINE_STRIDE_REG 0x1c28 412 #define DC_WINC_A_LINE_STRIDE_UV_LINE_STRIDE __BITS(31,16) 413 #define DC_WINC_A_LINE_STRIDE_LINE_STRIDE __BITS(15,0) 414 415 #define DC_WINC_A_DV_CONTROL_REG 0x1c38 416 #define DC_WINC_A_BLEND_LAYER_CONTROL_REG 0x1c58 417 #define DC_WINC_A_BLEND_MATCH_SELECT_REG 0x1c5c 418 #define DC_WINC_A_BLEND_NOMATCH_SELECT_REG 0x1c60 419 #define DC_WINC_A_BLEND_ALPHA_1BIT_REG 0x1c64 420 421 /* 422 * WINBUF_A registers 423 */ 424 #define DC_WINBUF_A_START_ADDR_REG 0x2000 425 #define DC_WINBUF_A_START_ADDR_NS_REG 0x2004 426 #define DC_WINBUF_A_START_ADDR_U_REG 0x2008 427 #define DC_WINBUF_A_START_ADDR_U_NS_REG 0x200c 428 #define DC_WINBUF_A_START_ADDR_V_REG 0x2010 429 #define DC_WINBUF_A_START_ADDR_V_NS_REG 0x2014 430 #define DC_WINBUF_A_ADDR_H_OFFSET_REG 0x2018 431 #define DC_WINBUF_A_ADDR_H_OFFSET_NS_REG 0x201c 432 #define DC_WINBUF_A_ADDR_V_OFFSET_REG 0x2020 433 #define DC_WINBUF_A_ADDR_V_OFFSET_NS_REG 0x2024 434 #define DC_WINBUF_A_UFLOW_STATUS_REG 0x2028 435 436 #define DC_WINBUF_A_SURFACE_KIND_REG 0x202c 437 #define DC_WINBUF_A_SURFACE_KIND_BLOCK_HEIGHT __BITS(6,4) 438 #define DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND __BITS(1,0) 439 #define DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH 0 440 #define DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_TILED 1 441 #define DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_BL_16B2 2 442 443 #define DC_WINBUF_A_SURFACE_WEIGHT_REG 0x2030 444 #define DC_WINBUF_A_START_ADDR_HI_REG 0x2034 445 #define DC_WINBUF_A_START_ADDR_HI_NS_REG 0x2038 446 #define DC_WINBUF_A_START_ADDR_HI_U_REG 0x203c 447 #define DC_WINBUF_A_START_ADDR_HI_U_NS_REG 0x2040 448 #define DC_WINBUF_A_START_ADDR_HI_V_REG 0x2044 449 #define DC_WINBUF_A_START_ADDR_HI_V_NS_REG 0x2048 450 #define DC_WINBUF_A_START_ADDR_FIELD2_REG 0x204c 451 #define DC_WINBUF_A_START_ADDR_FIELD2_NS_REG 0x2050 452 #define DC_WINBUF_A_START_ADDR_FIELD2_U_REG 0x2054 453 #define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_REG 0x2058 454 #define DC_WINBUF_A_START_ADDR_FIELD2_V_REG 0x205c 455 #define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_REG 0x2060 456 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_REG 0x2064 457 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_REG 0x2068 458 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_REG 0x206c 459 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_REG 0x2070 460 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_REG 0x2074 461 #define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_REG 0x2078 462 #define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_REG 0x207c 463 #define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_REG 0x2080 464 #define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_REG 0x2084 465 #define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_REG 0x2088 466 #define DC_WINBUF_A_UFLOW_CTRL_REG 0x2090 467 #define DC_WINBUF_A_UFLOW_DBG_PIXEL_REG 0x2094 468 #define DC_WINBUF_A_UFLOW_THRESHOLD_REG 0x2098 469 #define DC_WINBUF_A_SPOOL_UP_REG 0x209c 470 #define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_REG 0x20a0 471 #define DC_WINBUF_A_LATENCY_THRESHOLD_REG 0x20a4 472 #define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_REG 0x20a8 473 #define DC_WINBUF_A_MEMFETCH_CONTROL_REG 0x20ac 474 #define DC_WINBUF_A_OCCUPANCY_THROTTLE_REG 0x20b0 475 #define DC_WINBUF_A_SCRATCH_REGISTER_0_REG 0x20b4 476 #define DC_WINBUF_A_SCRATCH_REGISTER_1_REG 0x20b8 477 478 479 #endif /* _ARM_TEGRA_DCREG_H */ 480