1 /* $NetBSD: tegra_clock.h,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_CLOCK_H 30 #define _ARM_TEGRA_CLOCK_H 31 32 enum tegra_clk_type { 33 TEGRA_CLK_FIXED, 34 TEGRA_CLK_PLL, 35 TEGRA_CLK_MUX, 36 TEGRA_CLK_FIXED_DIV, 37 TEGRA_CLK_DIV, 38 TEGRA_CLK_GATE 39 }; 40 41 struct tegra_fixed_clk { 42 u_int rate; 43 }; 44 45 struct tegra_fixed_div_clk { 46 u_int div; 47 }; 48 49 struct tegra_pll_clk { 50 u_int base_reg; 51 u_int divm_mask; 52 u_int divn_mask; 53 u_int divp_mask; 54 }; 55 56 struct tegra_mux_clk { 57 const char **parents; 58 u_int nparents; 59 u_int reg; 60 u_int bits; 61 }; 62 63 struct tegra_div_clk { 64 u_int reg; 65 u_int bits; 66 }; 67 68 struct tegra_gate_clk { 69 u_int set_reg; 70 u_int clr_reg; 71 u_int bits; 72 }; 73 74 struct tegra_clk { 75 struct clk base; /* must be first */ 76 u_int id; 77 const char *parent; 78 enum tegra_clk_type type; 79 u_int refcnt; 80 union { 81 struct tegra_fixed_clk fixed; 82 struct tegra_pll_clk pll; 83 struct tegra_mux_clk mux; 84 struct tegra_fixed_div_clk fixed_div; 85 struct tegra_div_clk div; 86 struct tegra_gate_clk gate; 87 } u; 88 }; 89 90 #define TEGRA_CLK_BASE(_tclk) ((_tclk) ? &(_tclk)->base : NULL) 91 #define TEGRA_CLK_PRIV(_clk) ((struct tegra_clk *)(_clk)) 92 93 #endif /* _ARM_TEGRA_CLOCK_H */ 94