1 /* $NetBSD: tegra_ahcisata.c,v 1.12 2018/12/14 12:29:22 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.12 2018/12/14 12:29:22 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/ahcisatavar.h> 41 42 #include <arm/nvidia/tegra_var.h> 43 #include <arm/nvidia/tegra_pmcreg.h> 44 #include <arm/nvidia/tegra_ahcisatareg.h> 45 #include <arm/nvidia/tegra_xusbpad.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 #define TEGRA_AHCISATA_OFFSET 0x7000 50 51 static int tegra_ahcisata_match(device_t, cfdata_t, void *); 52 static void tegra_ahcisata_attach(device_t, device_t, void *); 53 54 struct tegra_ahcisata_softc { 55 struct ahci_softc sc; 56 bus_space_tag_t sc_bst; 57 bus_space_handle_t sc_bsh; 58 void *sc_ih; 59 60 int sc_phandle; 61 struct clk *sc_clk_sata; 62 struct clk *sc_clk_sata_oob; 63 struct clk *sc_clk_cml1; 64 struct clk *sc_clk_pll_e; 65 struct fdtbus_reset *sc_rst_sata; 66 struct fdtbus_reset *sc_rst_sata_oob; 67 struct fdtbus_reset *sc_rst_sata_cold; 68 69 struct tegra_gpio_pin *sc_pin_power; 70 71 struct tegra_ahcisata_data 72 *sc_tad; 73 }; 74 75 static const char * const tegra124_ahcisata_supplies[] = { 76 "hvdd-supply", 77 "vddio-supply", 78 "avdd-supply", 79 "target-5v-supply", 80 "target-12v-supply" 81 }; 82 83 enum tegra_ahcisata_type { 84 TEGRA124, 85 TEGRA210 86 }; 87 88 struct tegra_ahcisata_data { 89 enum tegra_ahcisata_type tad_type; 90 const char * const * tad_supplies; 91 size_t tad_nsupplies; 92 }; 93 94 struct tegra_ahcisata_data tegra124_ahcisata_data = { 95 .tad_type = TEGRA124, 96 .tad_supplies = tegra124_ahcisata_supplies, 97 .tad_nsupplies = __arraycount(tegra124_ahcisata_supplies), 98 }; 99 100 struct tegra_ahcisata_data tegra210_ahcisata_data = { 101 .tad_type = TEGRA210, 102 }; 103 104 105 static const struct of_compat_data compat_data[] = { 106 { "nvidia,tegra124-ahci", (uintptr_t)&tegra124_ahcisata_data }, 107 { "nvidia,tegra210-ahci", (uintptr_t)&tegra210_ahcisata_data }, 108 { NULL }, 109 }; 110 111 112 static void tegra_ahcisata_init(struct tegra_ahcisata_softc *); 113 static int tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *); 114 115 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc), 116 tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL); 117 118 static int 119 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux) 120 { 121 struct fdt_attach_args * const faa = aux; 122 123 return of_match_compat_data(faa->faa_phandle, compat_data); 124 } 125 126 static void 127 tegra_ahcisata_attach(device_t parent, device_t self, void *aux) 128 { 129 struct tegra_ahcisata_softc * const sc = device_private(self); 130 struct fdt_attach_args * const faa = aux; 131 const int phandle = faa->faa_phandle; 132 bus_addr_t ahci_addr, sata_addr; 133 bus_size_t ahci_size, sata_size; 134 struct fdtbus_regulator *reg; 135 char intrstr[128]; 136 int error, n; 137 138 if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) { 139 aprint_error(": couldn't get ahci registers\n"); 140 return; 141 } 142 if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) { 143 aprint_error(": couldn't get sata registers\n"); 144 return; 145 } 146 sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata"); 147 if (sc->sc_clk_sata == NULL) { 148 aprint_error(": couldn't get clock sata\n"); 149 return; 150 } 151 sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob"); 152 if (sc->sc_clk_sata_oob == NULL) { 153 aprint_error(": couldn't get clock sata-oob\n"); 154 return; 155 } 156 sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata"); 157 if (sc->sc_rst_sata == NULL) { 158 aprint_error(": couldn't get reset sata\n"); 159 return; 160 } 161 sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob"); 162 if (sc->sc_rst_sata_oob == NULL) { 163 aprint_error(": couldn't get reset sata-oob\n"); 164 return; 165 } 166 sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold"); 167 if(sc->sc_rst_sata_cold == NULL) { 168 aprint_error(": couldn't get reset sata-cold\n"); 169 return; 170 } 171 172 uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data; 173 sc->sc_tad = (struct tegra_ahcisata_data *)data; 174 if (sc->sc_tad->tad_type == TEGRA124) { 175 sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1"); 176 if (sc->sc_clk_cml1 == NULL) { 177 aprint_error(": couldn't get clock cml1\n"); 178 return; 179 } 180 sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e"); 181 if (sc->sc_clk_pll_e == NULL) { 182 aprint_error(": couldn't get clock pll_e\n"); 183 return; 184 } 185 } 186 187 sc->sc_bst = faa->faa_bst; 188 error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh); 189 if (error) { 190 aprint_error(": couldn't map sata registers: %d\n", error); 191 return; 192 } 193 194 sc->sc_phandle = faa->faa_phandle; 195 sc->sc.sc_atac.atac_dev = self; 196 sc->sc.sc_dmat = faa->faa_dmat; 197 sc->sc.sc_ahcit = faa->faa_bst; 198 sc->sc.sc_ahcis = ahci_size; 199 error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0, 200 &sc->sc.sc_ahcih); 201 if (error) { 202 aprint_error(": couldn't map ahci registers: %d\n", error); 203 return; 204 } 205 sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET; 206 207 aprint_naive("\n"); 208 aprint_normal(": SATA\n"); 209 210 for (n = 0; n < sc->sc_tad->tad_nsupplies; n++) { 211 const char *supply = sc->sc_tad->tad_supplies[n]; 212 reg = fdtbus_regulator_acquire(phandle, supply); 213 if (reg == NULL) { 214 aprint_error_dev(self, "couldn't acquire %s\n", supply); 215 continue; 216 } 217 if (fdtbus_regulator_enable(reg) != 0) { 218 aprint_error_dev(self, "couldn't enable %s\n", supply); 219 } 220 fdtbus_regulator_release(reg); 221 } 222 223 if (tegra_ahcisata_init_clocks(sc) != 0) 224 return; 225 226 tegra_xusbpad_sata_enable(); 227 228 tegra_ahcisata_init(sc); 229 230 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 231 aprint_error_dev(self, "failed to decode interrupt\n"); 232 return; 233 } 234 235 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 236 ahci_intr, &sc->sc); 237 if (sc->sc_ih == NULL) { 238 aprint_error_dev(self, "failed to establish interrupt on %s\n", 239 intrstr); 240 return; 241 } 242 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 243 244 ahci_attach(&sc->sc); 245 } 246 247 static void 248 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc) 249 { 250 bus_space_tag_t bst = sc->sc_bst; 251 bus_space_handle_t bsh = sc->sc_bsh; 252 253 /* Set RX idle detection source and disable RX idle detection interrupt */ 254 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 255 TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0); 256 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG, 257 TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0); 258 259 /* Prevent automatic OOB sequence when coming out of reset */ 260 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 261 0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR); 262 263 /* Disable device sleep */ 264 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 265 0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT); 266 267 /* Enable IFPS device block */ 268 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG, 269 TEGRA_SATA_CONFIGURATION_EN_FPCI, 0); 270 271 /* Electrical settings for better link stability */ 272 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL17_REG, 0x55010000); 273 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL18_REG, 0x55010000); 274 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL20_REG, 1); 275 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL21_REG, 1); 276 277 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_0_REG, 278 TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH, 279 TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD); 280 281 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_NVOOB_REG, 282 __SHIFTIN(0x7, TEGRA_T_SATA0_NVOOB_COMMA_CNT) | 283 __SHIFTIN(0x3, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH) | 284 __SHIFTIN(0x1, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE), 285 TEGRA_T_SATA0_NVOOB_COMMA_CNT | 286 TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH | 287 TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE); 288 289 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_2NVOOB_2_REG, 290 __SHIFTIN(0xc, TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW), 291 TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW); 292 293 if (sc->sc_tad->tad_type == TEGRA124) { 294 const u_int gen1_tx_amp = 0x18; 295 const u_int gen1_tx_peak = 0x04; 296 const u_int gen2_tx_amp = 0x18; 297 const u_int gen2_tx_peak = 0x0a; 298 299 /* PHY config */ 300 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 301 TEGRA_T_SATA0_INDEX_CH1); 302 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG, 303 __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) | 304 __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK), 305 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP | 306 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK); 307 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG, 308 __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) | 309 __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK), 310 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP | 311 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK); 312 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG, 313 __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ)); 314 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG, 315 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1)); 316 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0); 317 } 318 319 /* Backdoor update the programming interface field and class code */ 320 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 321 TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0); 322 323 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG, 324 __SHIFTIN(0x0106, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) | 325 __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF)); 326 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 327 0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN); 328 329 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG, 330 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP | 331 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM | 332 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP | 333 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP, 0); 334 335 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_1_REG, 336 TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN | 337 TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN, 0); 338 339 /* Enable IFPS device block */ 340 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG, 341 0, TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE); 342 343 /* Enable access and bus mastering */ 344 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG, 345 TEGRA_T_SATA0_CFG1_SERR | 346 TEGRA_T_SATA0_CFG1_BUS_MASTER | 347 TEGRA_T_SATA0_CFG1_MEM_SPACE | 348 TEGRA_T_SATA0_CFG1_IO_SPACE, 349 0); 350 351 /* MMIO setup */ 352 bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG, 353 __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START) | 354 TEGRA_SATA_FPCI_BAR_ACCESS_TYPE); 355 356 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG, 357 __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS)); 358 359 /* Enable interrupts */ 360 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG, 361 TEGRA_SATA_INTR_MASK_IP_INT, 0); 362 } 363 364 static int 365 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc) 366 { 367 device_t self = sc->sc.sc_atac.atac_dev; 368 int error; 369 370 /* Assert resets */ 371 fdtbus_reset_assert(sc->sc_rst_sata); 372 fdtbus_reset_assert(sc->sc_rst_sata_cold); 373 374 /* Set SATA_OOB clock source to 204MHz */ 375 error = clk_set_rate(sc->sc_clk_sata_oob, 204000000); 376 if (error) { 377 aprint_error_dev(self, "couldn't set sata-oob rate: %d\n", 378 error); 379 return error; 380 } 381 382 /* Set SATA clock source to 102MHz */ 383 error = clk_set_rate(sc->sc_clk_sata, 102000000); 384 if (error) { 385 aprint_error_dev(self, "couldn't set sata rate: %d\n", error); 386 return error; 387 } 388 389 /* Ungate SAX partition in the PMC */ 390 tegra_pmc_power(PMC_PARTID_SAX, true); 391 delay(20); 392 393 /* Remove clamping from SAX partition in the PMC */ 394 tegra_pmc_remove_clamping(PMC_PARTID_SAX); 395 delay(20); 396 397 /* Un-gate clocks for SATA */ 398 error = clk_enable(sc->sc_clk_sata); 399 if (error) { 400 aprint_error_dev(self, "couldn't enable sata: %d\n", error); 401 return error; 402 } 403 error = clk_enable(sc->sc_clk_sata_oob); 404 if (error) { 405 aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error); 406 return error; 407 } 408 409 if (sc->sc_clk_cml1) { 410 /* Enable CML clock for SATA */ 411 error = clk_enable(sc->sc_clk_cml1); 412 if (error) { 413 aprint_error_dev(self, "couldn't enable cml1: %d\n", error); 414 return error; 415 } 416 } 417 418 /* Enable PHYs */ 419 struct fdtbus_phy *phy; 420 for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++) 421 if (fdtbus_phy_enable(phy, true) != 0) 422 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 423 424 /* De-assert resets */ 425 fdtbus_reset_deassert(sc->sc_rst_sata); 426 fdtbus_reset_deassert(sc->sc_rst_sata_cold); 427 428 return 0; 429 } 430