1 /* $NetBSD: tegra_ahcisata.c,v 1.18 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.18 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38
39 #include <dev/ata/atavar.h>
40 #include <dev/ic/ahcisatavar.h>
41
42 #include <arm/nvidia/tegra_var.h>
43 #include <arm/nvidia/tegra_pmcreg.h>
44 #include <arm/nvidia/tegra_ahcisatareg.h>
45 #include <arm/nvidia/tegra_xusbpad.h>
46
47 #include <dev/fdt/fdtvar.h>
48
49 #define TEGRA_AHCISATA_OFFSET 0x7000
50
51 static int tegra_ahcisata_match(device_t, cfdata_t, void *);
52 static void tegra_ahcisata_attach(device_t, device_t, void *);
53
54 struct tegra_ahcisata_softc {
55 struct ahci_softc sc;
56 bus_space_tag_t sc_bst;
57 bus_space_handle_t sc_bsh;
58 void *sc_ih;
59
60 int sc_phandle;
61 struct clk *sc_clk_sata;
62 struct clk *sc_clk_sata_oob;
63 struct clk *sc_clk_cml1;
64 struct clk *sc_clk_pll_e;
65 struct fdtbus_reset *sc_rst_sata;
66 struct fdtbus_reset *sc_rst_sata_oob;
67 struct fdtbus_reset *sc_rst_sata_cold;
68
69 struct tegra_gpio_pin *sc_pin_power;
70
71 const struct tegra_ahcisata_data
72 *sc_tad;
73 };
74
75 static const char * const tegra124_ahcisata_supplies[] = {
76 "hvdd-supply",
77 "vddio-supply",
78 "avdd-supply",
79 "target-5v-supply",
80 "target-12v-supply"
81 };
82
83 enum tegra_ahcisata_type {
84 TEGRA124,
85 TEGRA210
86 };
87
88 struct tegra_ahcisata_data {
89 enum tegra_ahcisata_type tad_type;
90 const char * const * tad_supplies;
91 size_t tad_nsupplies;
92 };
93
94 struct tegra_ahcisata_data tegra124_ahcisata_data = {
95 .tad_type = TEGRA124,
96 .tad_supplies = tegra124_ahcisata_supplies,
97 .tad_nsupplies = __arraycount(tegra124_ahcisata_supplies),
98 };
99
100 struct tegra_ahcisata_data tegra210_ahcisata_data = {
101 .tad_type = TEGRA210,
102 };
103
104
105 static const struct device_compatible_entry compat_data[] = {
106 { .compat = "nvidia,tegra124-ahci", .data = &tegra124_ahcisata_data },
107 { .compat = "nvidia,tegra210-ahci", .data = &tegra210_ahcisata_data },
108 DEVICE_COMPAT_EOL,
109 };
110
111
112 static void tegra_ahcisata_init(struct tegra_ahcisata_softc *);
113 static int tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *);
114
115 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc),
116 tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL);
117
118 static int
tegra_ahcisata_match(device_t parent,cfdata_t cf,void * aux)119 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux)
120 {
121 struct fdt_attach_args * const faa = aux;
122
123 return of_compatible_match(faa->faa_phandle, compat_data);
124 }
125
126 static void
tegra_ahcisata_attach(device_t parent,device_t self,void * aux)127 tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
128 {
129 struct tegra_ahcisata_softc * const sc = device_private(self);
130 struct fdt_attach_args * const faa = aux;
131 const int phandle = faa->faa_phandle;
132 bus_addr_t ahci_addr, sata_addr;
133 bus_size_t ahci_size, sata_size;
134 struct fdtbus_regulator *reg;
135 char intrstr[128];
136 int error, n;
137
138 if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) {
139 aprint_error(": couldn't get ahci registers\n");
140 return;
141 }
142 if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) {
143 aprint_error(": couldn't get sata registers\n");
144 return;
145 }
146 sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata");
147 if (sc->sc_clk_sata == NULL) {
148 aprint_error(": couldn't get clock sata\n");
149 return;
150 }
151 sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob");
152 if (sc->sc_clk_sata_oob == NULL) {
153 aprint_error(": couldn't get clock sata-oob\n");
154 return;
155 }
156 sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata");
157 if (sc->sc_rst_sata == NULL) {
158 aprint_error(": couldn't get reset sata\n");
159 return;
160 }
161 sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob");
162 if (sc->sc_rst_sata_oob == NULL) {
163 aprint_error(": couldn't get reset sata-oob\n");
164 return;
165 }
166 sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold");
167 if(sc->sc_rst_sata_cold == NULL) {
168 aprint_error(": couldn't get reset sata-cold\n");
169 return;
170 }
171
172 sc->sc_tad = of_compatible_lookup(faa->faa_phandle, compat_data)->data;
173 if (sc->sc_tad->tad_type == TEGRA124) {
174 sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1");
175 if (sc->sc_clk_cml1 == NULL) {
176 aprint_error(": couldn't get clock cml1\n");
177 return;
178 }
179 sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e");
180 if (sc->sc_clk_pll_e == NULL) {
181 aprint_error(": couldn't get clock pll_e\n");
182 return;
183 }
184 }
185
186 sc->sc_bst = faa->faa_bst;
187 error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh);
188 if (error) {
189 aprint_error(": couldn't map sata registers: %d\n", error);
190 return;
191 }
192
193 sc->sc_phandle = faa->faa_phandle;
194 sc->sc.sc_atac.atac_dev = self;
195 sc->sc.sc_dmat = faa->faa_dmat;
196 sc->sc.sc_ahcit = faa->faa_bst;
197 sc->sc.sc_ahcis = ahci_size;
198 error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0,
199 &sc->sc.sc_ahcih);
200 if (error) {
201 aprint_error(": couldn't map ahci registers: %d\n", error);
202 return;
203 }
204
205 aprint_naive("\n");
206 aprint_normal(": SATA\n");
207
208 for (n = 0; n < sc->sc_tad->tad_nsupplies; n++) {
209 const char *supply = sc->sc_tad->tad_supplies[n];
210 reg = fdtbus_regulator_acquire(phandle, supply);
211 if (reg == NULL) {
212 aprint_error_dev(self, "couldn't acquire %s\n", supply);
213 continue;
214 }
215 if (fdtbus_regulator_enable(reg) != 0) {
216 aprint_error_dev(self, "couldn't enable %s\n", supply);
217 }
218 fdtbus_regulator_release(reg);
219 }
220
221 if (tegra_ahcisata_init_clocks(sc) != 0)
222 return;
223
224 tegra_xusbpad_sata_enable();
225
226 tegra_ahcisata_init(sc);
227
228 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
229 aprint_error_dev(self, "failed to decode interrupt\n");
230 return;
231 }
232
233 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_BIO, 0,
234 ahci_intr, &sc->sc, device_xname(self));
235 if (sc->sc_ih == NULL) {
236 aprint_error_dev(self, "failed to establish interrupt on %s\n",
237 intrstr);
238 return;
239 }
240 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
241
242 ahci_attach(&sc->sc);
243 }
244
245 static void
tegra_ahcisata_init(struct tegra_ahcisata_softc * sc)246 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc)
247 {
248 bus_space_tag_t bst = sc->sc_bst;
249 bus_space_handle_t bsh = sc->sc_bsh;
250
251 /* Set RX idle detection source and disable RX idle detection interrupt */
252 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
253 TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0);
254 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG,
255 TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0);
256
257 /* Prevent automatic OOB sequence when coming out of reset */
258 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
259 0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR);
260
261 /* Disable device sleep */
262 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
263 0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT);
264
265 /* Enable IFPS device block */
266 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
267 TEGRA_SATA_CONFIGURATION_EN_FPCI, 0);
268
269 /* Electrical settings for better link stability */
270 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL17_REG, 0x55010000);
271 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL18_REG, 0x55010000);
272 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL20_REG, 1);
273 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL21_REG, 1);
274
275 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_0_REG,
276 TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH,
277 TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD);
278
279 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_NVOOB_REG,
280 __SHIFTIN(0x7, TEGRA_T_SATA0_NVOOB_COMMA_CNT) |
281 __SHIFTIN(0x3, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH) |
282 __SHIFTIN(0x1, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE),
283 TEGRA_T_SATA0_NVOOB_COMMA_CNT |
284 TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
285 TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
286
287 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_2NVOOB_2_REG,
288 __SHIFTIN(0xc, TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW),
289 TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW);
290
291 if (sc->sc_tad->tad_type == TEGRA124) {
292 const u_int gen1_tx_amp = 0x18;
293 const u_int gen1_tx_peak = 0x04;
294 const u_int gen2_tx_amp = 0x18;
295 const u_int gen2_tx_peak = 0x0a;
296
297 /* PHY config */
298 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG,
299 TEGRA_T_SATA0_INDEX_CH1);
300 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG,
301 __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) |
302 __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK),
303 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP |
304 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK);
305 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG,
306 __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) |
307 __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK),
308 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP |
309 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK);
310 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG,
311 __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ));
312 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG,
313 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));
314 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0);
315 }
316
317 /* Backdoor update the programming interface field and class code */
318 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
319 TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0);
320
321 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG,
322 __SHIFTIN(0x0106, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |
323 __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF));
324 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
325 0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN);
326
327 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG,
328 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
329 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM |
330 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
331 TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP, 0);
332
333 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_1_REG,
334 TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
335 TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN, 0);
336
337 /* Enable IFPS device block */
338 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
339 0, TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE);
340
341 /* Enable access and bus mastering */
342 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG,
343 TEGRA_T_SATA0_CFG1_SERR |
344 TEGRA_T_SATA0_CFG1_BUS_MASTER |
345 TEGRA_T_SATA0_CFG1_MEM_SPACE |
346 TEGRA_T_SATA0_CFG1_IO_SPACE,
347 0);
348
349 /* MMIO setup */
350 bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG,
351 __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START) |
352 TEGRA_SATA_FPCI_BAR_ACCESS_TYPE);
353
354 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG,
355 __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));
356
357 /* Enable interrupts */
358 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG,
359 TEGRA_SATA_INTR_MASK_IP_INT, 0);
360 }
361
362 static int
tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc * sc)363 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc)
364 {
365 device_t self = sc->sc.sc_atac.atac_dev;
366 int error;
367
368 /* Assert resets */
369 fdtbus_reset_assert(sc->sc_rst_sata);
370 fdtbus_reset_assert(sc->sc_rst_sata_cold);
371
372 /* Set SATA_OOB clock source to 204MHz */
373 error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);
374 if (error) {
375 aprint_error_dev(self, "couldn't set sata-oob rate: %d\n",
376 error);
377 return error;
378 }
379
380 /* Set SATA clock source to 102MHz */
381 error = clk_set_rate(sc->sc_clk_sata, 102000000);
382 if (error) {
383 aprint_error_dev(self, "couldn't set sata rate: %d\n", error);
384 return error;
385 }
386
387 /* Ungate SAX partition in the PMC */
388 tegra_pmc_power(PMC_PARTID_SAX, true);
389 delay(20);
390
391 /* Remove clamping from SAX partition in the PMC */
392 tegra_pmc_remove_clamping(PMC_PARTID_SAX);
393 delay(20);
394
395 /* Un-gate clocks for SATA */
396 error = clk_enable(sc->sc_clk_sata);
397 if (error) {
398 aprint_error_dev(self, "couldn't enable sata: %d\n", error);
399 return error;
400 }
401 error = clk_enable(sc->sc_clk_sata_oob);
402 if (error) {
403 aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error);
404 return error;
405 }
406
407 if (sc->sc_clk_cml1) {
408 /* Enable CML clock for SATA */
409 error = clk_enable(sc->sc_clk_cml1);
410 if (error) {
411 aprint_error_dev(self, "couldn't enable cml1: %d\n", error);
412 return error;
413 }
414 }
415
416 /* Enable PHYs */
417 struct fdtbus_phy *phy;
418 for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++)
419 if (fdtbus_phy_enable(phy, true) != 0)
420 aprint_error_dev(self, "failed to enable PHY #%d\n", n);
421
422 /* De-assert resets */
423 fdtbus_reset_deassert(sc->sc_rst_sata);
424 fdtbus_reset_deassert(sc->sc_rst_sata_cold);
425
426 return 0;
427 }
428