1 /* $NetBSD: tegra_ahcisata.c,v 1.11 2017/09/19 20:46:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.11 2017/09/19 20:46:12 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/ahcisatavar.h> 41 42 #include <arm/nvidia/tegra_var.h> 43 #include <arm/nvidia/tegra_pmcreg.h> 44 #include <arm/nvidia/tegra_ahcisatareg.h> 45 #include <arm/nvidia/tegra_xusbpad.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 #define TEGRA_AHCISATA_OFFSET 0x7000 50 51 static int tegra_ahcisata_match(device_t, cfdata_t, void *); 52 static void tegra_ahcisata_attach(device_t, device_t, void *); 53 54 struct tegra_ahcisata_softc { 55 struct ahci_softc sc; 56 bus_space_tag_t sc_bst; 57 bus_space_handle_t sc_bsh; 58 void *sc_ih; 59 struct clk *sc_clk_sata; 60 struct clk *sc_clk_sata_oob; 61 struct clk *sc_clk_cml1; 62 struct clk *sc_clk_pll_e; 63 struct fdtbus_reset *sc_rst_sata; 64 struct fdtbus_reset *sc_rst_sata_oob; 65 struct fdtbus_reset *sc_rst_sata_cold; 66 67 struct tegra_gpio_pin *sc_pin_power; 68 }; 69 70 static const char * const tegra_ahcisata_supplies[] = { 71 "hvdd-supply", 72 "vddio-supply", 73 "avdd-supply", 74 "target-5v-supply", 75 "target-12v-supply" 76 }; 77 78 static void tegra_ahcisata_init(struct tegra_ahcisata_softc *); 79 static int tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *); 80 81 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc), 82 tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL); 83 84 static int 85 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux) 86 { 87 const char * const compatible[] = { "nvidia,tegra124-ahci", NULL }; 88 struct fdt_attach_args * const faa = aux; 89 90 return of_match_compatible(faa->faa_phandle, compatible); 91 } 92 93 static void 94 tegra_ahcisata_attach(device_t parent, device_t self, void *aux) 95 { 96 struct tegra_ahcisata_softc * const sc = device_private(self); 97 struct fdt_attach_args * const faa = aux; 98 const int phandle = faa->faa_phandle; 99 bus_addr_t ahci_addr, sata_addr; 100 bus_size_t ahci_size, sata_size; 101 struct fdtbus_regulator *reg; 102 char intrstr[128]; 103 int error, n; 104 105 if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) { 106 aprint_error(": couldn't get ahci registers\n"); 107 return; 108 } 109 if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) { 110 aprint_error(": couldn't get sata registers\n"); 111 return; 112 } 113 sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata"); 114 if (sc->sc_clk_sata == NULL) { 115 aprint_error(": couldn't get clock sata\n"); 116 return; 117 } 118 sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob"); 119 if (sc->sc_clk_sata_oob == NULL) { 120 aprint_error(": couldn't get clock sata-oob\n"); 121 return; 122 } 123 sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1"); 124 if (sc->sc_clk_cml1 == NULL) { 125 aprint_error(": couldn't get clock cml1\n"); 126 return; 127 } 128 sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e"); 129 if (sc->sc_clk_pll_e == NULL) { 130 aprint_error(": couldn't get clock pll_e\n"); 131 return; 132 } 133 sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata"); 134 if (sc->sc_rst_sata == NULL) { 135 aprint_error(": couldn't get reset sata\n"); 136 return; 137 } 138 sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob"); 139 if (sc->sc_rst_sata_oob == NULL) { 140 aprint_error(": couldn't get reset sata-oob\n"); 141 return; 142 } 143 sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold"); 144 if(sc->sc_rst_sata_cold == NULL) { 145 aprint_error(": couldn't get reset sata-cold\n"); 146 return; 147 } 148 149 sc->sc_bst = faa->faa_bst; 150 error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh); 151 if (error) { 152 aprint_error(": couldn't map sata registers: %d\n", error); 153 return; 154 } 155 156 sc->sc.sc_atac.atac_dev = self; 157 sc->sc.sc_dmat = faa->faa_dmat; 158 sc->sc.sc_ahcit = faa->faa_bst; 159 sc->sc.sc_ahcis = ahci_size; 160 error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0, 161 &sc->sc.sc_ahcih); 162 if (error) { 163 aprint_error(": couldn't map ahci registers: %d\n", error); 164 return; 165 } 166 sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET; 167 168 aprint_naive("\n"); 169 aprint_normal(": SATA\n"); 170 171 for (n = 0; n < __arraycount(tegra_ahcisata_supplies); n++) { 172 const char *supply = tegra_ahcisata_supplies[n]; 173 reg = fdtbus_regulator_acquire(phandle, supply); 174 if (reg == NULL) { 175 aprint_error_dev(self, "couldn't acquire %s\n", supply); 176 continue; 177 } 178 if (fdtbus_regulator_enable(reg) != 0) { 179 aprint_error_dev(self, "couldn't enable %s\n", supply); 180 } 181 fdtbus_regulator_release(reg); 182 } 183 184 if (tegra_ahcisata_init_clocks(sc) != 0) 185 return; 186 187 tegra_xusbpad_sata_enable(); 188 189 tegra_ahcisata_init(sc); 190 191 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 192 aprint_error_dev(self, "failed to decode interrupt\n"); 193 return; 194 } 195 196 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 197 ahci_intr, &sc->sc); 198 if (sc->sc_ih == NULL) { 199 aprint_error_dev(self, "failed to establish interrupt on %s\n", 200 intrstr); 201 return; 202 } 203 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 204 205 ahci_attach(&sc->sc); 206 } 207 208 static void 209 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc) 210 { 211 bus_space_tag_t bst = sc->sc_bst; 212 bus_space_handle_t bsh = sc->sc_bsh; 213 214 const u_int gen1_tx_amp = 0x18; 215 const u_int gen1_tx_peak = 0x04; 216 const u_int gen2_tx_amp = 0x18; 217 const u_int gen2_tx_peak = 0x0a; 218 219 /* Set RX idle detection source and disable RX idle detection interrupt */ 220 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 221 TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0); 222 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG, 223 TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0); 224 225 /* Prevent automatic OOB sequence when coming out of reset */ 226 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 227 0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR); 228 229 /* Disable device sleep */ 230 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 231 0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT); 232 233 /* Enable IFPS device block */ 234 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG, 235 TEGRA_SATA_CONFIGURATION_EN_FPCI, 0); 236 237 /* PHY config */ 238 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 239 TEGRA_T_SATA0_INDEX_CH1); 240 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG, 241 __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) | 242 __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK), 243 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP | 244 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK); 245 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG, 246 __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) | 247 __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK), 248 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP | 249 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK); 250 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG, 251 __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ)); 252 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG, 253 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1)); 254 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0); 255 256 /* Backdoor update the programming interface field and class code */ 257 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 258 TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0); 259 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG, 260 __SHIFTIN(0x1016, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) | 261 __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF)); 262 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 263 0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN); 264 265 /* Enable access and bus mastering */ 266 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG, 267 TEGRA_T_SATA0_CFG1_SERR | 268 TEGRA_T_SATA0_CFG1_BUS_MASTER | 269 TEGRA_T_SATA0_CFG1_MEM_SPACE | 270 TEGRA_T_SATA0_CFG1_IO_SPACE, 271 0); 272 273 /* MMIO setup */ 274 bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG, 275 __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START)); 276 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG, 277 __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS)); 278 279 /* Enable interrupts */ 280 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG, 281 TEGRA_SATA_INTR_MASK_IP_INT, 0); 282 } 283 284 static int 285 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc) 286 { 287 device_t self = sc->sc.sc_atac.atac_dev; 288 int error; 289 290 /* Assert resets */ 291 fdtbus_reset_assert(sc->sc_rst_sata); 292 fdtbus_reset_assert(sc->sc_rst_sata_cold); 293 294 /* Set SATA_OOB clock source to 204MHz */ 295 error = clk_set_rate(sc->sc_clk_sata_oob, 204000000); 296 if (error) { 297 aprint_error_dev(self, "couldn't set sata-oob rate: %d\n", 298 error); 299 return error; 300 } 301 302 /* Set SATA clock source to 102MHz */ 303 error = clk_set_rate(sc->sc_clk_sata, 102000000); 304 if (error) { 305 aprint_error_dev(self, "couldn't set sata rate: %d\n", error); 306 return error; 307 } 308 309 /* Ungate SAX partition in the PMC */ 310 tegra_pmc_power(PMC_PARTID_SAX, true); 311 delay(20); 312 313 /* Remove clamping from SAX partition in the PMC */ 314 tegra_pmc_remove_clamping(PMC_PARTID_SAX); 315 delay(20); 316 317 /* Un-gate clocks and enable CML clock for SATA */ 318 error = clk_enable(sc->sc_clk_sata); 319 if (error) { 320 aprint_error_dev(self, "couldn't enable sata: %d\n", error); 321 return error; 322 } 323 error = clk_enable(sc->sc_clk_sata_oob); 324 if (error) { 325 aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error); 326 return error; 327 } 328 error = clk_enable(sc->sc_clk_cml1); 329 if (error) { 330 aprint_error_dev(self, "couldn't enable cml1: %d\n", error); 331 return error; 332 } 333 334 /* De-assert resets */ 335 fdtbus_reset_deassert(sc->sc_rst_sata); 336 fdtbus_reset_deassert(sc->sc_rst_sata_cold); 337 338 return 0; 339 } 340