1 /* $NetBSD: tegra_ahcisata.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/ahcisatavar.h> 41 42 #include <arm/nvidia/tegra_var.h> 43 #include <arm/nvidia/tegra_ahcisatareg.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define TEGRA_AHCISATA_OFFSET 0x7000 48 49 static int tegra_ahcisata_match(device_t, cfdata_t, void *); 50 static void tegra_ahcisata_attach(device_t, device_t, void *); 51 52 struct tegra_ahcisata_softc { 53 struct ahci_softc sc; 54 bus_space_tag_t sc_bst; 55 bus_space_handle_t sc_bsh; 56 void *sc_ih; 57 58 struct tegra_gpio_pin *sc_pin_power; 59 }; 60 61 static const char * const tegra_ahcisata_supplies[] = { 62 "hvdd-supply", 63 "vddio-supply", 64 "avdd-supply", 65 "target-5v-supply", 66 "target-12v-supply" 67 }; 68 69 static void tegra_ahcisata_init(struct tegra_ahcisata_softc *); 70 71 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc), 72 tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL); 73 74 static int 75 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux) 76 { 77 const char * const compatible[] = { "nvidia,tegra124-ahci", NULL }; 78 struct fdt_attach_args * const faa = aux; 79 80 return of_match_compatible(faa->faa_phandle, compatible); 81 } 82 83 static void 84 tegra_ahcisata_attach(device_t parent, device_t self, void *aux) 85 { 86 struct tegra_ahcisata_softc * const sc = device_private(self); 87 struct fdt_attach_args * const faa = aux; 88 const int phandle = faa->faa_phandle; 89 bus_addr_t ahci_addr, sata_addr; 90 bus_size_t ahci_size, sata_size; 91 struct fdtbus_regulator *reg; 92 char intrstr[128]; 93 int error, n; 94 95 if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) { 96 aprint_error(": couldn't get ahci registers\n"); 97 return; 98 } 99 if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) { 100 aprint_error(": couldn't get sata registers\n"); 101 return; 102 } 103 104 sc->sc_bst = faa->faa_bst; 105 error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh); 106 if (error) { 107 aprint_error(": couldn't map sata registers: %d\n", error); 108 return; 109 } 110 111 sc->sc.sc_atac.atac_dev = self; 112 sc->sc.sc_dmat = faa->faa_dmat; 113 sc->sc.sc_ahcit = faa->faa_bst; 114 sc->sc.sc_ahcis = ahci_size; 115 error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0, 116 &sc->sc.sc_ahcih); 117 if (error) { 118 aprint_error(": couldn't map ahci registers: %d\n", error); 119 return; 120 } 121 sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET; 122 123 aprint_naive("\n"); 124 aprint_normal(": SATA\n"); 125 126 for (n = 0; n < __arraycount(tegra_ahcisata_supplies); n++) { 127 const char *supply = tegra_ahcisata_supplies[n]; 128 reg = fdtbus_regulator_acquire(phandle, supply); 129 if (reg == NULL) { 130 aprint_error_dev(self, "couldn't acquire %s\n", supply); 131 continue; 132 } 133 if (fdtbus_regulator_enable(reg) != 0) { 134 aprint_error_dev(self, "couldn't enable %s\n", supply); 135 } 136 fdtbus_regulator_release(reg); 137 } 138 139 tegra_car_periph_sata_enable(); 140 141 tegra_xusbpad_sata_enable(); 142 143 tegra_ahcisata_init(sc); 144 145 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 146 aprint_error_dev(self, "failed to decode interrupt\n"); 147 return; 148 } 149 150 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 151 ahci_intr, &sc->sc); 152 if (sc->sc_ih == NULL) { 153 aprint_error_dev(self, "failed to establish interrupt on %s\n", 154 intrstr); 155 return; 156 } 157 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 158 159 ahci_attach(&sc->sc); 160 } 161 162 static void 163 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc) 164 { 165 bus_space_tag_t bst = sc->sc_bst; 166 bus_space_handle_t bsh = sc->sc_bsh; 167 168 const u_int gen1_tx_amp = 0x18; 169 const u_int gen1_tx_peak = 0x04; 170 const u_int gen2_tx_amp = 0x18; 171 const u_int gen2_tx_peak = 0x0a; 172 173 /* Set RX idle detection source and disable RX idle detection interrupt */ 174 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 175 TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0); 176 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG, 177 TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0); 178 179 /* Prevent automatic OOB sequence when coming out of reset */ 180 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 181 0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR); 182 183 /* Disable device sleep */ 184 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 185 0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT); 186 187 /* Enable IFPS device block */ 188 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG, 189 TEGRA_SATA_CONFIGURATION_EN_FPCI, 0); 190 191 /* PHY config */ 192 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 193 TEGRA_T_SATA0_INDEX_CH1); 194 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG, 195 __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) | 196 __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK), 197 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP | 198 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK); 199 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG, 200 __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) | 201 __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK), 202 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP | 203 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK); 204 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG, 205 __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ)); 206 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG, 207 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1)); 208 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0); 209 210 /* Backdoor update the programming interface field and class code */ 211 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 212 TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0); 213 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG, 214 __SHIFTIN(0x1016, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) | 215 __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF)); 216 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 217 0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN); 218 219 /* Enable access and bus mastering */ 220 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG, 221 TEGRA_T_SATA0_CFG1_SERR | 222 TEGRA_T_SATA0_CFG1_BUS_MASTER | 223 TEGRA_T_SATA0_CFG1_MEM_SPACE | 224 TEGRA_T_SATA0_CFG1_IO_SPACE, 225 0); 226 227 /* MMIO setup */ 228 bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG, 229 __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START)); 230 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG, 231 __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS)); 232 233 /* Enable interrupts */ 234 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG, 235 TEGRA_SATA_INTR_MASK_IP_INT, 0); 236 } 237