1 /* $NetBSD: tegra124_xusbpad.c,v 1.2 2017/09/22 20:25:51 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra124_xusbpad.c,v 1.2 2017/09/22 20:25:51 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_xusbpad.h> 43 #include <arm/nvidia/tegra124_xusbpadreg.h> 44 #include <arm/nvidia/tegra_var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define TEGRA_FUSE_SKU_CALIB_REG 0xf0 49 50 static int tegra124_xusbpad_match(device_t, cfdata_t, void *); 51 static void tegra124_xusbpad_attach(device_t, device_t, void *); 52 static void tegra124_xusbpad_sata_enable(device_t); 53 static void tegra124_xusbpad_xhci_enable(device_t); 54 55 static const struct tegra_xusbpad_ops tegra124_xusbpad_ops = { 56 .sata_enable = tegra124_xusbpad_sata_enable, 57 .xhci_enable = tegra124_xusbpad_xhci_enable, 58 }; 59 60 struct tegra124_xusbpad_softc { 61 device_t sc_dev; 62 bus_space_tag_t sc_bst; 63 bus_space_handle_t sc_bsh; 64 }; 65 66 #ifdef TEGRA_XUSBPAD_DEBUG 67 static void padregdump(void); 68 #endif 69 70 CFATTACH_DECL_NEW(tegra124_xusbpad, sizeof(struct tegra124_xusbpad_softc), 71 tegra124_xusbpad_match, tegra124_xusbpad_attach, NULL, NULL); 72 73 static int 74 tegra124_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 75 { 76 const char * const compatible[] = 77 { "nvidia,tegra124-xusb-padctl", NULL }; 78 struct fdt_attach_args * const faa = aux; 79 80 return of_match_compatible(faa->faa_phandle, compatible); 81 } 82 83 static void 84 tegra124_xusbpad_attach(device_t parent, device_t self, void *aux) 85 { 86 struct tegra124_xusbpad_softc * const sc = device_private(self); 87 struct fdt_attach_args * const faa = aux; 88 bus_addr_t addr; 89 bus_size_t size; 90 int error; 91 92 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 93 aprint_error(": couldn't get registers\n"); 94 return; 95 } 96 97 sc->sc_dev = self; 98 sc->sc_bst = faa->faa_bst; 99 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 100 if (error) { 101 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 102 return; 103 } 104 105 aprint_naive("\n"); 106 aprint_normal(": XUSB PADCTL\n"); 107 108 tegra_xusbpad_register(self, &tegra124_xusbpad_ops); 109 } 110 111 static void 112 tegra124_xusbpad_sata_enable(device_t dev) 113 { 114 struct tegra124_xusbpad_softc * const sc = device_private(dev); 115 bus_space_tag_t bst = sc->sc_bst; 116 bus_space_handle_t bsh = sc->sc_bsh; 117 int retry; 118 119 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG, 120 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA, 121 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) | 122 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0, 123 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0); 124 125 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG, 126 0, 127 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ | 128 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD); 129 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 130 0, 131 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ | 132 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD); 133 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 134 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0); 135 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 136 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0); 137 138 for (retry = 1000; retry > 0; retry--) { 139 const uint32_t v = bus_space_read_4(bst, bsh, 140 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG); 141 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 142 break; 143 delay(100); 144 } 145 if (retry == 0) { 146 printf("WARNING: SATA PHY power-on failed\n"); 147 } 148 } 149 150 #ifdef TEGRA_XUSBPAD_DEBUG 151 static void 152 padregdump(void) 153 { 154 bus_space_tag_t bst; 155 bus_space_handle_t bsh; 156 bus_size_t i; 157 u_int j; 158 159 tegra124_xusbpad_get_bs(&bst, &bsh); 160 161 for (i = 0x000; i < 0x160; ) { 162 printf("0x%03jx:", (uintmax_t)i); 163 for (j = 0; i < 0x160 && j < 0x10; j += 4, i += 4) { 164 printf(" %08x", bus_space_read_4(bst, bsh, i)); 165 } 166 printf("\n"); 167 } 168 } 169 #endif 170 171 static void 172 tegra124_xusbpad_xhci_enable(device_t dev) 173 { 174 struct tegra124_xusbpad_softc * const sc = device_private(dev); 175 const uint32_t skucalib = tegra_fuse_read(TEGRA_FUSE_SKU_CALIB_REG); 176 #ifdef TEGRA_XUSBPAD_DEBUG 177 uint32_t val; 178 #endif 179 180 if (sc == NULL) { 181 aprint_error("%s: xusbpad driver not loaded\n", __func__); 182 return; 183 } 184 185 186 #ifdef TEGRA_XUSBPAD_DEBUG 187 padregdump(void); 188 printf("SKU CALIB 0x%x\n", skucalib); 189 #endif 190 const uint32_t hcl[3] = { 191 (skucalib >> 0) & 0x3f, 192 (skucalib >> 15) & 0x3f, 193 (skucalib >> 15) & 0x3f, 194 }; 195 const uint32_t hic = (skucalib >> 13) & 3; 196 const uint32_t hsl = (skucalib >> 11) & 3; 197 const uint32_t htra = (skucalib >> 7) & 0xf; 198 199 200 #ifdef TEGRA_XUSBPAD_DEBUG 201 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 202 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 203 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 204 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 205 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 206 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 207 #endif 208 209 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG, (0<<0)|(0<<2)|(1<<4)); 210 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG, (1<<0)|(1<<4)|(1<<8)); 211 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG, (2<<0)|(7<<4)); 212 213 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 214 __SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) | 215 __SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL, 216 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL), 217 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL | 218 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL); 219 220 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 221 XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 222 __SHIFTIN(hcl[0], 223 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 224 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 225 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 226 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0), 227 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 228 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 229 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 230 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 231 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 232 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 233 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 234 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 235 XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 236 __SHIFTIN(hcl[1], 237 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 238 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 239 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 240 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1), 241 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 242 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 243 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 244 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 245 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 246 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 247 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 248 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 249 XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 250 __SHIFTIN(hcl[2], 251 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 252 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 253 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 254 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2), 255 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 256 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 257 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 258 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 259 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 260 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 261 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 262 263 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 264 XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 265 __SHIFTIN(htra, 266 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 267 __SHIFTIN(hic, 268 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 269 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 270 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 271 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 272 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 273 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 274 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 275 XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 276 __SHIFTIN(htra, 277 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 278 __SHIFTIN(hic, 279 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 280 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 281 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 282 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 283 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 284 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 285 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 286 XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 287 __SHIFTIN(htra, 288 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 289 __SHIFTIN(hic, 290 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 291 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 292 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 293 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 294 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 295 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 296 297 //tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG, 0, 1); /* PD_OTG */ 298 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 299 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 300 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 301 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 302 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 303 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 304 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 305 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 306 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 307 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 308 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 309 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 310 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD); 311 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK); 312 313 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 314 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN); 315 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 316 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY); 317 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 318 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN); 319 320 DELAY(200); 321 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, 322 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN); 323 DELAY(200); 324 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, 325 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY); 326 DELAY(200); 327 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, 328 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN); 329 DELAY(200); 330 331 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 0, 332 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD2 | 333 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD1 | 334 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD0 | 335 XUSB_PADCTL_OC_DET_OC_DETECTED3 | 336 XUSB_PADCTL_OC_DET_OC_DETECTED2 | 337 XUSB_PADCTL_OC_DET_OC_DETECTED1 | 338 XUSB_PADCTL_OC_DET_OC_DETECTED0); 339 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 340 XUSB_PADCTL_OC_DET_VBUS_ENABLE2 | 341 XUSB_PADCTL_OC_DET_VBUS_ENABLE1 | 342 XUSB_PADCTL_OC_DET_VBUS_ENABLE0, 0); 343 344 #ifdef TEGRA_XUSBPAD_DEBUG 345 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 346 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 347 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 348 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 349 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 350 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 351 352 padregdump(); 353 #endif 354 } 355