1 /* $NetBSD: tegra124_xusbpad.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_tegra.h"
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: tegra124_xusbpad.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $");
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40
41 #include <arm/nvidia/tegra_reg.h>
42 #include <arm/nvidia/tegra_xusbpad.h>
43 #include <arm/nvidia/tegra124_xusbpadreg.h>
44 #include <arm/nvidia/tegra_var.h>
45
46 #include <dev/fdt/fdtvar.h>
47
48 #define TEGRA_FUSE_SKU_CALIB_REG 0xf0
49
50 static int tegra124_xusbpad_match(device_t, cfdata_t, void *);
51 static void tegra124_xusbpad_attach(device_t, device_t, void *);
52 static void tegra124_xusbpad_sata_enable(device_t);
53 static void tegra124_xusbpad_xhci_enable(device_t);
54
55 static const struct tegra_xusbpad_ops tegra124_xusbpad_ops = {
56 .sata_enable = tegra124_xusbpad_sata_enable,
57 .xhci_enable = tegra124_xusbpad_xhci_enable,
58 };
59
60 struct tegra124_xusbpad_softc {
61 device_t sc_dev;
62 bus_space_tag_t sc_bst;
63 bus_space_handle_t sc_bsh;
64 };
65
66 #ifdef TEGRA_XUSBPAD_DEBUG
67 static void padregdump(void);
68 #endif
69
70 CFATTACH_DECL_NEW(tegra124_xusbpad, sizeof(struct tegra124_xusbpad_softc),
71 tegra124_xusbpad_match, tegra124_xusbpad_attach, NULL, NULL);
72
73 static const struct device_compatible_entry compat_data[] = {
74 { .compat = "nvidia,tegra124-xusb-padctl" },
75 DEVICE_COMPAT_EOL
76 };
77
78 static int
tegra124_xusbpad_match(device_t parent,cfdata_t cf,void * aux)79 tegra124_xusbpad_match(device_t parent, cfdata_t cf, void *aux)
80 {
81 struct fdt_attach_args * const faa = aux;
82
83 return of_compatible_match(faa->faa_phandle, compat_data);
84 }
85
86 static void
tegra124_xusbpad_attach(device_t parent,device_t self,void * aux)87 tegra124_xusbpad_attach(device_t parent, device_t self, void *aux)
88 {
89 struct tegra124_xusbpad_softc * const sc = device_private(self);
90 struct fdt_attach_args * const faa = aux;
91 bus_addr_t addr;
92 bus_size_t size;
93 int error;
94
95 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
96 aprint_error(": couldn't get registers\n");
97 return;
98 }
99
100 sc->sc_dev = self;
101 sc->sc_bst = faa->faa_bst;
102 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
103 if (error) {
104 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
105 return;
106 }
107
108 aprint_naive("\n");
109 aprint_normal(": XUSB PADCTL\n");
110
111 tegra_xusbpad_register(self, &tegra124_xusbpad_ops);
112 }
113
114 static void
tegra124_xusbpad_sata_enable(device_t dev)115 tegra124_xusbpad_sata_enable(device_t dev)
116 {
117 struct tegra124_xusbpad_softc * const sc = device_private(dev);
118 bus_space_tag_t bst = sc->sc_bst;
119 bus_space_handle_t bsh = sc->sc_bsh;
120 int retry;
121
122 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG,
123 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA,
124 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) |
125 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0,
126 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0);
127
128 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG,
129 0,
130 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ |
131 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD);
132 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
133 0,
134 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ |
135 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD);
136 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
137 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0);
138 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
139 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0);
140
141 for (retry = 1000; retry > 0; retry--) {
142 const uint32_t v = bus_space_read_4(bst, bsh,
143 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG);
144 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
145 break;
146 delay(100);
147 }
148 if (retry == 0) {
149 printf("WARNING: SATA PHY power-on failed\n");
150 }
151 }
152
153 #ifdef TEGRA_XUSBPAD_DEBUG
154 static void
padregdump(void)155 padregdump(void)
156 {
157 bus_space_tag_t bst;
158 bus_space_handle_t bsh;
159 bus_size_t i;
160 u_int j;
161
162 tegra124_xusbpad_get_bs(&bst, &bsh);
163
164 for (i = 0x000; i < 0x160; ) {
165 printf("0x%03jx:", (uintmax_t)i);
166 for (j = 0; i < 0x160 && j < 0x10; j += 4, i += 4) {
167 printf(" %08x", bus_space_read_4(bst, bsh, i));
168 }
169 printf("\n");
170 }
171 }
172 #endif
173
174 static void
tegra124_xusbpad_xhci_enable(device_t dev)175 tegra124_xusbpad_xhci_enable(device_t dev)
176 {
177 struct tegra124_xusbpad_softc * const sc = device_private(dev);
178 const uint32_t skucalib = tegra_fuse_read(TEGRA_FUSE_SKU_CALIB_REG);
179 #ifdef TEGRA_XUSBPAD_DEBUG
180 uint32_t val;
181 #endif
182
183 if (sc == NULL) {
184 aprint_error("%s: xusbpad driver not loaded\n", __func__);
185 return;
186 }
187
188
189 #ifdef TEGRA_XUSBPAD_DEBUG
190 padregdump(void);
191 printf("SKU CALIB 0x%x\n", skucalib);
192 #endif
193 const uint32_t hcl[3] = {
194 (skucalib >> 0) & 0x3f,
195 (skucalib >> 15) & 0x3f,
196 (skucalib >> 15) & 0x3f,
197 };
198 const uint32_t hic = (skucalib >> 13) & 3;
199 const uint32_t hsl = (skucalib >> 11) & 3;
200 const uint32_t htra = (skucalib >> 7) & 0xf;
201
202
203 #ifdef TEGRA_XUSBPAD_DEBUG
204 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG);
205 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val);
206 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG);
207 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val);
208 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG);
209 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val);
210 #endif
211
212 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG, (0<<0)|(0<<2)|(1<<4));
213 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG, (1<<0)|(1<<4)|(1<<8));
214 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG, (2<<0)|(7<<4));
215
216 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG,
217 __SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) |
218 __SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL,
219 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL),
220 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL |
221 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL);
222
223 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
224 XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG,
225 __SHIFTIN(hcl[0],
226 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) |
227 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,
228 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) |
229 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0),
230 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW),
231 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL |
232 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW |
233 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW |
234 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
235 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
236 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
237 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
238 XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG,
239 __SHIFTIN(hcl[1],
240 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) |
241 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,
242 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) |
243 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1),
244 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW),
245 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL |
246 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW |
247 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW |
248 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
249 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
250 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
251 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
252 XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG,
253 __SHIFTIN(hcl[2],
254 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) |
255 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,
256 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) |
257 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2),
258 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW),
259 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL |
260 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW |
261 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW |
262 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
263 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
264 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
265
266 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
267 XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG,
268 __SHIFTIN(htra,
269 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) |
270 __SHIFTIN(hic,
271 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP),
272 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ |
273 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP |
274 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
275 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP |
276 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP);
277 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
278 XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG,
279 __SHIFTIN(htra,
280 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) |
281 __SHIFTIN(hic,
282 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP),
283 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ |
284 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP |
285 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
286 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP |
287 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP);
288 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
289 XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG,
290 __SHIFTIN(htra,
291 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) |
292 __SHIFTIN(hic,
293 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP),
294 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ |
295 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP |
296 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
297 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP |
298 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP);
299
300 //tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG, 0, 1); /* PD_OTG */
301 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD);
302 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD);
303 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD);
304 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2);
305 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2);
306 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2);
307 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
308 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
309 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
310 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR);
311 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR);
312 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR);
313 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD);
314 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK);
315
316 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG,
317 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN);
318 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG,
319 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY);
320 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG,
321 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN);
322
323 DELAY(200);
324 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0,
325 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN);
326 DELAY(200);
327 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0,
328 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY);
329 DELAY(200);
330 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0,
331 XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN);
332 DELAY(200);
333
334 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 0,
335 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD2 |
336 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD1 |
337 XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD0 |
338 XUSB_PADCTL_OC_DET_OC_DETECTED3 |
339 XUSB_PADCTL_OC_DET_OC_DETECTED2 |
340 XUSB_PADCTL_OC_DET_OC_DETECTED1 |
341 XUSB_PADCTL_OC_DET_OC_DETECTED0);
342 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG,
343 XUSB_PADCTL_OC_DET_VBUS_ENABLE2 |
344 XUSB_PADCTL_OC_DET_VBUS_ENABLE1 |
345 XUSB_PADCTL_OC_DET_VBUS_ENABLE0, 0);
346
347 #ifdef TEGRA_XUSBPAD_DEBUG
348 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG);
349 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val);
350 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG);
351 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val);
352 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG);
353 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val);
354
355 padregdump();
356 #endif
357 }
358