1 /* $NetBSD: mvsocpmu.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
2 /*
3 * Copyright (c) 2016 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: mvsocpmu.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $");
29
30 #include "opt_mvsoc.h"
31
32 #include <sys/param.h>
33 #include <sys/device.h>
34 #include <sys/errno.h>
35
36 #include <dev/sysmon/sysmonvar.h>
37
38 #include <arm/marvell/mvsocreg.h>
39 #include <arm/marvell/mvsocvar.h>
40 #include <arm/marvell/mvsocpmuvar.h>
41
42 #include <dev/marvell/marvellreg.h>
43 #include <dev/marvell/marvellvar.h>
44
45 #define UC2UK(uc) ((uc) + 273150000)
46 #define UK2UC(uk) ((uk) - 273150000)
47
48 #define MVSOCPMU_TM_CSR 0x0 /* Control and Status Register */
49 #define TM_CSR_TMDIS (1 << 0) /* Thermal Manager Disable */
50 #define TM_CSR_THERMTEMPOUT(v) (((v) >> 1) & 0x1ff)/* Current Temperature */
51 #define TM_CSR_THR(oh, c) ((((oh) & 0x1ff) << 19)|(((c) & 0x1ff) << 10))
52 #define TM_CSR_COOLTHR_MASK (0x1ff << 10)
53 #define TM_CSR_OVERHEATTHR_MASK (0x1ff << 19)
54 #define TM_CSR_COOLTHR(v) (((v) >> 10) & 0x1ff) /* Cooling Threshold */
55 #define TM_CSR_OVERHEATTHR(v) (((v) >> 19) & 0x1ff)/* Over Heat Threshold */
56 #define MVSOCPMU_TM_CDR 0x4 /* Cooling Delay Register */
57 #define MVSOCPMU_TM_ODR 0x8 /* Overheat Delay Register */
58
59 #define MVSOCPMU_TM_READ(sc, r) \
60 bus_space_read_4((sc)->sc_iot, (sc)->sc_tmh, _TM_REG(r))
61 #define MVSOCPMU_TM_WRITE(sc, r, v) \
62 bus_space_write_4((sc)->sc_iot, (sc)->sc_tmh, _TM_REG(r), (v))
63 #define _TM_REG(r) MVSOCPMU_TM_ ## r
64
65 static void mvsocpmu_tm_init(struct mvsocpmu_softc *);
66 static void mvsocpmu_tm_refresh(struct sysmon_envsys *, envsys_data_t *);
67 static void mvsocpmu_tm_get_limits(struct sysmon_envsys *, envsys_data_t *,
68 sysmon_envsys_lim_t *, uint32_t *);
69 static void mvsocpmu_tm_set_limits(struct sysmon_envsys *, envsys_data_t *,
70 sysmon_envsys_lim_t *, uint32_t *);
71
72 /* ARGSUSED */
73 int
mvsocpmu_match(device_t parent,struct cfdata * match,void * aux)74 mvsocpmu_match(device_t parent, struct cfdata *match, void *aux)
75 {
76 struct marvell_attach_args *mva = aux;
77
78 if (strcmp(mva->mva_name, match->cf_name) != 0)
79 return 0;
80 return 1;
81 }
82
83 /* ARGSUSED */
84 void
mvsocpmu_attach(device_t parent,device_t self,void * aux)85 mvsocpmu_attach(device_t parent, device_t self, void *aux)
86 {
87 struct mvsocpmu_softc *sc = device_private(self);
88
89 aprint_naive("\n");
90 aprint_normal(": Marvell SoC Power Management Unit\n");
91
92 sc->sc_dev = self;
93
94 if (sc->sc_val2uc != NULL && sc->sc_uc2val != NULL)
95 mvsocpmu_tm_init(sc);
96 }
97
98 static void
mvsocpmu_tm_init(struct mvsocpmu_softc * sc)99 mvsocpmu_tm_init(struct mvsocpmu_softc *sc)
100 {
101 uint32_t csr;
102
103 /* set default thresholds */
104 csr = MVSOCPMU_TM_READ(sc, CSR);
105 sc->sc_deflims.sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
106 sc->sc_deflims.sel_warnmax =
107 UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
108 sc->sc_defprops = PROP_WARNMIN | PROP_WARNMAX;
109
110 sc->sc_sme = sysmon_envsys_create();
111 /* Initialize sensor data. */
112 sc->sc_sensor.units = ENVSYS_STEMP;
113 sc->sc_sensor.state = ENVSYS_SINVALID;
114 sc->sc_sensor.flags = ENVSYS_FMONLIMITS;
115 strlcpy(sc->sc_sensor.desc, device_xname(sc->sc_dev),
116 sizeof(sc->sc_sensor.desc));
117 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) {
118 aprint_error_dev(sc->sc_dev, "Unable to attach sysmon\n");
119 sysmon_envsys_destroy(sc->sc_sme);
120 return;
121 }
122
123 /* Hook into system monitor. */
124 sc->sc_sme->sme_name = device_xname(sc->sc_dev);
125 sc->sc_sme->sme_cookie = sc;
126 sc->sc_sme->sme_refresh = mvsocpmu_tm_refresh;
127 sc->sc_sme->sme_get_limits = mvsocpmu_tm_get_limits;
128 sc->sc_sme->sme_set_limits = mvsocpmu_tm_set_limits;
129 if (sysmon_envsys_register(sc->sc_sme)) {
130 aprint_error_dev(sc->sc_dev,
131 "Unable to register with sysmon\n");
132 sysmon_envsys_destroy(sc->sc_sme);
133 }
134 }
135
136 static void
mvsocpmu_tm_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)137 mvsocpmu_tm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
138 {
139 struct mvsocpmu_softc *sc = sme->sme_cookie;
140 uint32_t csr, uc, uk;
141
142 csr = MVSOCPMU_TM_READ(sc, CSR);
143 if (csr & TM_CSR_TMDIS) {
144 sc->sc_sensor.state = ENVSYS_SINVALID;
145 return;
146 }
147 uc = sc->sc_val2uc(TM_CSR_THERMTEMPOUT(csr)); /* uC */
148 uk = UC2UK(uc); /* convert to uKelvin */
149 sc->sc_sensor.value_cur = uk;
150 sc->sc_sensor.state = ENVSYS_SVALID;
151 }
152
153 static void
mvsocpmu_tm_get_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)154 mvsocpmu_tm_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
155 sysmon_envsys_lim_t *limits, uint32_t *props)
156 {
157 struct mvsocpmu_softc *sc = sme->sme_cookie;
158 uint32_t csr;
159
160 csr = MVSOCPMU_TM_READ(sc, CSR);
161 limits->sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
162 limits->sel_warnmax = UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
163 *props = (PROP_WARNMIN | PROP_WARNMAX | PROP_DRIVER_LIMITS);
164 }
165
166 static void
mvsocpmu_tm_set_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)167 mvsocpmu_tm_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
168 sysmon_envsys_lim_t *limits, uint32_t *props)
169 {
170 struct mvsocpmu_softc *sc = sme->sme_cookie;
171 uint32_t csr, mask;
172 int oh, c;
173
174 if (limits == NULL) {
175 limits = &sc->sc_deflims;
176 props = &sc->sc_defprops;
177 }
178 oh = c = 0;
179 mask = 0x0;
180 if (*props & PROP_WARNMIN) {
181 c = sc->sc_uc2val(UK2UC(limits->sel_warnmin));
182 mask |= TM_CSR_COOLTHR_MASK;
183 }
184 if (*props & PROP_WARNMAX) {
185 oh = sc->sc_uc2val(UK2UC(limits->sel_warnmax));
186 mask |= TM_CSR_OVERHEATTHR_MASK;
187 }
188 if (mask != 0) {
189 csr = MVSOCPMU_TM_READ(sc, CSR);
190 csr &= ~mask;
191 MVSOCPMU_TM_WRITE(sc, CSR, csr | TM_CSR_THR(oh, c));
192 }
193
194 /*
195 * If at least one limit is set that we can handle, and no
196 * limits are set that we cannot handle, tell sysmon that
197 * the driver will take care of monitoring the limits!
198 */
199 if (*props & (PROP_WARNMIN | PROP_WARNMAX))
200 *props |= PROP_DRIVER_LIMITS;
201 else
202 *props &= ~PROP_DRIVER_LIMITS;
203 }
204