1 /* $NetBSD: imxsdmareg.h,v 1.3 2024/10/07 15:04:32 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi and Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _IMXSDMAREG_H 30 #define _IMXSDMAREG_H 31 32 #include "opt_imx.h" 33 34 #define SDMA_SIZE 0x2c0 35 36 /* SDMA Controller */ 37 #define SDMA_N_CHANNELS 32 38 #define SDMA_PRIORITY_MIN 1 39 #define SDMA_PRIORITY_MAX 7 40 41 #define SDMA_N_EVENTS 32 /* DMA events from peripherals */ 42 43 #define SDMA_MC0PTR 0x0000 44 #define SDMA_INTR 0x0004 45 #define SDMA_STOP_STAT 0x0008 46 #define SDMA_HSTART 0x000C 47 #define SDMA_EVTOVR 0x0010 48 #define SDMA_DSPOVR 0x0014 49 #define SDMA_HOSTOVR 0x0018 50 #define SDMA_EVTPEND 0x001C 51 #define SDMA_RESET 0x0024 52 #define SDMA_RESET_RESCHED __BIT(1) 53 #define SDMA_RESET_RESET __BIT(0) 54 #define SDMA_EVTERR 0x0028 55 #define SDMA_INTRMASK 0x002C 56 #define SDMA_PSW 0x0030 57 #define SDMA_EVTERRDBG 0x0034 58 #define SDMA_CONFIG 0x0038 59 #define SDMA_ONCE_ENB 0x0040 60 #define SDMA_ONCE_DATA 0x0044 61 #define SDMA_ONCE_INSTR 0x0048 62 #define SDMA_ONCE_STAT 0x004c 63 #define ONCE_STAT_PST_SHIFT 12 64 #define ONCE_STAT_PST_MASK (0xf<<ONCE_STAT_PST_SHIFT) 65 #define ONCE_STAT_PST_PROGRAM (0<<ONCE_STAT_PST_SHIFT) 66 #define ONCE_STAT_PST_DATA (1<<ONCE_STAT_PST_SHIFT) 67 #define ONCE_STAT_PST_CHGFLOW (2<<ONCE_STAT_PST_SHIFT) 68 #define ONCE_STAT_PST_CHGFLOW_IN_LOOP (3<<ONCE_STAT_PST_SHIFT) 69 #define ONCE_STAT_PST_DEBUG (4<<ONCE_STAT_PST_SHIFT) 70 #define ONCE_STAT_PST_FUNCUNIT (5<<ONCE_STAT_PST_SHIFT) 71 #define ONCE_STAT_PST_SLEEP (6<<ONCE_STAT_PST_SHIFT) 72 #define ONCE_STAT_PST_SAVE (7<<ONCE_STAT_PST_SHIFT) 73 #define ONCE_STAT_PST_PROGRAM_IN_SLEEP (8<<ONCE_STAT_PST_SHIFT) 74 #define ONCE_STAT_PST_DATA_IN_SLEEP (9<<ONCE_STAT_PST_SHIFT) 75 #define ONCE_STAT_PST_CHGFLOW_IN_SLEEP (10<<ONCE_STAT_PST_SHIFT) 76 #define ONCE_STAT_PST_CHGFLOW_IN_LOOP_IN_SLEEP (10<<ONCE_STAT_PST_SHIFT) 77 #define ONCE_STAT_PST_DEBUG_IN_SLEEP (12<<ONCE_STAT_PST_SHIFT) 78 #define ONCE_STAT_PST_FUNCUNIT_IN_SLEEP (13<<ONCE_STAT_PST_SHIFT) 79 #define ONCE_STAT_PST_SLEEP_AFTER_RESET (14<<ONCE_STAT_PST_SHIFT) 80 #define ONCE_STAT_PST_RESTORE (15<<ONCE_STAT_PST_SHIFT) 81 82 #define ONCE_STAT_RCV __BIT(11) 83 #define ONCE_STAT_EDR __BIT(10) 84 #define ONCE_STAT_ODR __BIT(9) 85 #define ONCE_STAT_SWB __BIT(8) 86 #define ONCE_STAT_MST __BIT(7) 87 #define ONCE_STAT_ECDR 0X07 88 89 #define SDMA_ONCE_CMD 0x0050 90 #define ONCE_RSTATUS 0 91 #define ONCE_DMOV 1 92 #define ONCE_EXEC_ONCE 2 93 #define ONCE_RUN 3 94 #define ONCE_EXEC_CORE 4 95 #define ONCE_DEBUG_RQST 5 96 #define ONCE_RBUFFER 6 97 #define SDMA_EVT_MIRROR 0x0054 98 #define SDMA_ILLINSTADDR 0x0058 /* Illegal Instruction Trap Address */ 99 #define SDMA_CHN0ADDR 0x005c /* Channel 0 Boot address */ 100 #define SDMA_XTRIG_CONF1 0x0070 /* Cross-Triger Evennts Config */ 101 #define SDMA_XTRIG_CONF2 0x0074 102 #if defined(IMX31) 103 #define SDMA_CHNENBL(n) (0x80+(n)*4) /* Channel Enable RAM */ 104 #elif defined(IMX51) 105 #define SDMA_OTB 0x0078 106 #define SDMA_PRF_CNT(n) (0x07c+(n)*4) 107 #define SDMA_CHNENBL(n) (0x200+(n)*4) /* Channel Enable RAM */ 108 #endif 109 #define SDMA_CHNPRI(n) (0x100+(n)*4) /* Channel Priority */ 110 111 112 /* 113 * Memory of SDMA Risc Core 114 */ 115 116 #define SDMACORE_ROM_BASE 0x0000 117 #define SDMACORE_ROM_SIZE 0x0400 /* in 32-bit word. 4K bytes */ 118 #define SDMACORE_RAM_BASE 0x0800 119 #define SDMACORE_RAM_SIZE 0x0800 /* in 32-bit word. 8K byte */ 120 121 #define SDMACORE_CONTEXT_BASE 0x0800 122 #define SDMACORE_CONTEXT_SIZE 32 /* XXX: or 24 */ 123 #define SDMACORE_CONTEXT_ADDR(ch) (SDMACORE_CONTEXT_BASE+ \ 124 (SDMACORE_CONTEXT_SIZE * (ch))) 125 #define SDMACORE_CONTEXT_END SDMACORE_CONTEXT_ADDR(SDMA_N_CHANNELS) 126 127 128 #endif /* _IMXSDMAREG_H */ 129