1 /* $NetBSD: imx51_intr.h,v 1.4 2024/02/07 04:20:26 msaitoh Exp $ */ 2 /*- 3 * Copyright (c) 2009 SHIMIZU Ryo 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ARM_IMX_IMX51_INTR_H_ 28 #define _ARM_IMX_IMX51_INTR_H_ 29 30 #define IRQ_RSVD0 0 /* Reserved */ 31 #define IRQ_ESDHC1 1 /* Enhanced SDHC Interrupt Request */ 32 #define IRQ_ESDHC2 2 /* Enhanced SDHC Interrupt Request */ 33 #define IRQ_ESDHC3 3 /* CE-ATA Interrupt Request based on eSDHC-3 */ 34 #define IRQ_ESDHC4 4 /* Enhanced SDHC Interrupt Request */ 35 #define IRQ_DAP 5 /* Power-up Request */ 36 #define IRQ_SDMA 6 /* "AND" of all 48 interrupts from all the channels */ 37 #define IRQ_IOMUX 7 /* POWER FAIL interrupt */ 38 #define IRQ_EMI_NFC 8 /* nfc interrupt out */ 39 #define IRQ_VPU 9 /* VPU Interrupt Request */ 40 #define IRQ_IPUEXERR 10 /* IPUEX Error Interrupt */ 41 #define IRQ_IPUEXSYNC 11 /* IPUEX Sync Interrupt */ 42 #define IRQ_GPU3D 12 /* GPU3D Interrupt Request */ 43 #define IRQ_RSVD13 13 /* Reserved */ 44 #define IRQ_USBOH1 14 /* USB Host 1 */ 45 #define IRQ_EMI 15 /* Consolidated EMI Interrupt */ 46 #define IRQ_USBOH2 16 /* USB Host 2 */ 47 #define IRQ_USBOH3 17 /* USB Host 3 */ 48 #define IRQ_USBOH_OTG 18 /* USB OTG */ 49 #define IRQ_SAHARA0 19 /* SAHARA host 0 (TrustZone) Intr */ 50 #define IRQ_SAHARA1 20 /* SAHARA host 1 (non-TrustZone) Intr */ 51 #define IRQ_SCC_HIGH 21 /* Security Monitor High Priority Interrupt Request. */ 52 #define IRQ_SCC_SEC 22 /* Secure (TrustZone) Interrupt Request. */ 53 #define IRQ_SCC 23 /* Regular (Non-Secure) Interrupt Request. */ 54 #define IRQ_SRTC_CONS 24 /* SRTC Consolidated Interrupt. Non TZ. */ 55 #define IRQ_SRTC_SEC 25 /* SRTC Security Interrupt. TZ. */ 56 #define IRQ_RTIC 26 /* RTIC (Trust Zone) Interrupt Request. Indicates that the RTI selected memory block(s) during single-hash/boot mode. */ 57 #define IRQ_CSU 27 /* CSU Interrupt Request 1. Indicates to the processor that on asserted */ 58 #define IRQ_SLIMBUS 28 /* Slimbus Interrupt Request */ 59 #define IRQ_SSI1 29 /* SSI-1 Interrupt Request */ 60 #define IRQ_SSI2 30 /* SSI-2 Interrupt Request */ 61 #define IRQ_UART1 31 /* UART-1 ORed interrupt */ 62 #define IRQ_UART2 32 /* UART-2 ORed interrupt */ 63 #define IRQ_UART3 33 /* UART-3 ORed interrupt */ 64 #define IRQ_RSVD34 34 /* Reserved */ 65 #define IRQ_RSVD35 35 /* Reserved */ 66 #define IRQ_ECSPI1 36 /* eCSPI1 interrupt request line to the core. */ 67 #define IRQ_ECSPI2 37 /* eCSPI2 interrupt request line to the core. */ 68 #define IRQ_CSPI 38 /* CSPI interrupt request line to the core. */ 69 #define IRQ_GPT 39 /* "OR" of GPT Rollover interrupt line, Input Capture 1 and 2 lin 3 Interrupt lines" */ 70 #define IRQ_EPIT1 40 /* EPIT1 output compare interrupt */ 71 #define IRQ_EPIT2 41 /* EPIT2 output compare interrupt */ 72 #define IRQ_GPIO7 42 /* Active HIGH Interrupt from INT7 from GPIO */ 73 #define IRQ_GPIO6 43 /* Active HIGH Interrupt from INT6 from GPIO */ 74 #define IRQ_GPIO5 44 /* Active HIGH Interrupt from INT5 from GPIO */ 75 #define IRQ_GPIO4 45 /* Active HIGH Interrupt from INT4 from GPIO */ 76 #define IRQ_GPIO3 46 /* Active HIGH Interrupt from INT3 from GPIO */ 77 #define IRQ_GPIO2 47 /* Active HIGH Interrupt from INT2 from GPIO */ 78 #define IRQ_GPIO1 48 /* Active HIGH Interrupt from INT1 from GPIO */ 79 #define IRQ_GPIO0 49 /* Active HIGH Interrupt from INT0 from GPIO */ 80 #define IRQ_GPIO1_LOW 50 /* Combined interrupt indication for GPIO1 signal 0 throughout 15 */ 81 #define IRQ_GPIO1_HIGH 51 /* Combined interrupt indication for GPIO1 signal 16 throughout 31 */ 82 #define IRQ_GPIO2_LOW 52 /* Combined interrupt indication for GPIO2 signal 0 throughout 15 */ 83 #define IRQ_GPIO2_HIGH 53 /* Combined interrupt indication for GPIO2 signal 16 throughout 31 */ 84 #define IRQ_GPIO3_LOW 54 /* Combined interrupt indication for GPIO3 signal 0 throughout 15 */ 85 #define IRQ_GPIO3_HIGH 55 /* Combined interrupt indication for GPIO3 signal 16 throughout 31 */ 86 #define IRQ_GPIO4_LOW 56 /* Combined interrupt indication for GPIO4 signal 0 throughout 15 */ 87 #define IRQ_GPIO4_HIGH 57 /* Combined interrupt indication for GPIO4 signal 16 throughout 31 */ 88 #define IRQ_WDOG1 58 /* Watchdog Timer reset */ 89 #define IRQ_WDOG2 59 /* Watchdog Timer reset */ 90 #define IRQ_KPP 60 /* Keypad Interrupt */ 91 #define IRQ_PWM1 61 /* "Cumulative interrupt line. "OR" of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line." */ 92 #define IRQ_I2C1 62 /* I2C-1 Interrupt */ 93 #define IRQ_I2C2 63 /* I2C-2 Interrupt */ 94 #define IRQ_HS_I2C 64 /* High Speed I2C Interrupt */ 95 #define IRQ_RSVD65 65 /* Reserved */ 96 #define IRQ_RSVD66 66 /* Reserved */ 97 #define IRQ_SIM1 67 /* "SIM interrupt composed of oef, xte, sdi1, and sdi0" */ 98 #define IRQ_SIM2 68 /* "SIM interrupt composed of tc, etc, tfe, and rdrf" */ 99 #define IRQ_IIM 69 /* Interrupt request to the processor. Indicates to the processor that program or explicit sense cycle is completed successfully or in case of error. This signal is low-asserted. */ 100 #define IRQ_PATA 70 /* Parallel ATA host controller interrupt request */ 101 #define IRQ_CCM1 71 /* "CCM, Interrupt Request 1" */ 102 #define IRQ_CCM2 72 /* "CCM, Interrupt Request 2" */ 103 #define IRQ_GPC1 73 /* "GPC, Interrupt Request 1" */ 104 #define IRQ_GPC2 74 /* "GPC, Interrupt Request 2" */ 105 #define IRQ_SRC 75 /* SRC interrupt request */ 106 #define IRQ_NEON 76 /* Neon Monitor Interrupt */ 107 #define IRQ_PERFUNIT 77 /* Performance Unit Interrupt */ 108 #define IRQ_CTI 78 /* CTI IRQ */ 109 #define IRQ_DEBUG1 79 /* "Debug Interrupt, from Cross-Trigger Interface 1" */ 110 #define IRQ_DEBUG1B 80 /* "Debug Interrupt, from Cross-Trigger Interface 1" */ 111 #define IRQ_GPU2D 84 /* GPU2D (OpenVG) general interrupt */ 112 #define IRQ_GPU2D_BUSY 85 /* GPU2D (OpenVG) busy signal (for S/W power gating feasibility) */ 113 #define IRQ_RSVD86 86 /* Reserved */ 114 #define IRQ_FEC 87 /* Fast Ethernet Controller Interrupt request (OR of 13 interrupt sources) */ 115 #define IRQ_OWIRE 88 /* 1-Wire Interrupt Request */ 116 #define IRQ_DEBUG2 89 /* "Debug Interrupt, from Cross-Trigger Interface 2" */ 117 #define IRQ_SJC 90 /* SJC */ 118 #define IRQ_SPDIF 91 /* SPDIF */ 119 #define IRQ_TVE 92 /* TVE */ 120 #define IRQ_FIRI 93 /* FIRI Intr (OR of all 4 interrupt sources) */ 121 #define IRQ_PWM2 94 /* "Cumulative interrupt line. "OR" of Rollover Interrupt line, Compare Interrupt line and FIFO" */ 122 #define IRQ_SLIMBUS_E 95 /* Slimbus Interrupt Request (Exceptional cases) */ 123 #define IRQ_SSI3 96 /* SSI-3 Interrupt Request */ 124 #define IRQ_EMI_BOOT 97 /* Boot sequence completed interrupt */ 125 #define IRQ_DEBUG3 98 /* "Debug Interrupt, from Cross-Trigger Interface 3" */ 126 #define IRQ_RXSMC 99 /* Rx SMC receive interrupt (Generated whenever SLM receives a shared channel message) */ 127 #define IRQ_VPU_IDLE 100 /* Idle interrupt from VPU (for S/W power gating) */ 128 #define IRQ_EMI_TRNSFER 101 /* Indicates all pages have been transferred to NFC during an auto program operation. */ 129 #define IRQ_GPU3D_IDLE 102 /* Idle interrupt from GPU3D (for S/W power gating) */ 130 #define IRQ_RSVD103 103 /* Reserved */ 131 #define IRQ_RSVD104 104 /* Reserved */ 132 #define IRQ_RSVD105 105 /* Reserved */ 133 #define IRQ_RSVD106 106 /* Reserved */ 134 #define IRQ_RSVD107 107 /* Reserved */ 135 #define IRQ_RSVD108 108 /* Reserved */ 136 #define IRQ_RSVD109 109 /* Reserved */ 137 #define IRQ_RSVD110 110 /* Reserved */ 138 #define IRQ_RSVD111 111 /* Reserved */ 139 #define IRQ_RSVD112 112 /* Reserved */ 140 #define IRQ_RSVD113 113 /* Reserved */ 141 #define IRQ_RSVD114 114 /* Reserved */ 142 #define IRQ_RSVD115 115 /* Reserved */ 143 #define IRQ_RSVD116 116 /* Reserved */ 144 #define IRQ_RSVD117 117 /* Reserved */ 145 #define IRQ_RSVD118 118 /* Reserved */ 146 #define IRQ_RSVD119 119 /* Reserved */ 147 #define IRQ_RSVD120 120 /* Reserved */ 148 #define IRQ_RSVD121 121 /* Reserved */ 149 #define IRQ_RSVD122 122 /* Reserved */ 150 #define IRQ_RSVD123 123 /* Reserved */ 151 #define IRQ_RSVD124 124 /* Reserved */ 152 #define IRQ_RSVD125 125 /* Reserved */ 153 #define IRQ_RSVD126 126 /* Reserved */ 154 #define IRQ_RSVD127 127 /* Reserved */ 155 156 #ifdef _LOCORE 157 158 #define ARM_IRQ_HANDLER _C_LABEL(imx51_irq_handler) 159 160 #else 161 162 #define TZIC_INTR_SOURCE_NAMES \ 163 { "rsvd0", /* IRQ0 */ \ 164 "esdhc1", /* IRQ1 */ \ 165 "esdhc2", /* IRQ2 */ \ 166 "esdhc3", /* IRQ3 */ \ 167 "esdhc4", /* IRQ4 */ \ 168 "dap", /* IRQ5 */ \ 169 "sdma", /* IRQ6 */ \ 170 "iomux", /* IRQ7 */ \ 171 "emi", /* IRQ8 */ \ 172 "vpu", /* IRQ9 */ \ 173 "ipuexerr", /* IRQ10 */ \ 174 "ipuexsync", /* IRQ11 */ \ 175 "gpu3d", /* IRQ12 */ \ 176 "rsvd13", /* IRQ13 */ \ 177 "usboh1", /* IRQ14 */ \ 178 "emi", /* IRQ15 */ \ 179 "usboh2", /* IRQ16 */ \ 180 "usboh3", /* IRQ17 */ \ 181 "usboh3", /* IRQ18 */ \ 182 "sahara0", /* IRQ19 */ \ 183 "sahara1", /* IRQ20 */ \ 184 "scc_high", /* IRQ21 */ \ 185 "scc_sec", /* IRQ22 */ \ 186 "scc", /* IRQ23 */ \ 187 "srtc_cons", /* IRQ24 */ \ 188 "srtc_sec", /* IRQ25 */ \ 189 "rtic", /* IRQ26 */ \ 190 "csu", /* IRQ27 */ \ 191 "slimbus", /* IRQ28 */ \ 192 "ssi1", /* IRQ29 */ \ 193 "ssi2", /* IRQ30 */ \ 194 "uart1", /* IRQ31 */ \ 195 "uart2", /* IRQ32 */ \ 196 "uart3", /* IRQ33 */ \ 197 "rsvd34", /* IRQ34 */ \ 198 "rsvd35", /* IRQ35 */ \ 199 "ecspi1", /* IRQ36 */ \ 200 "ecspi2", /* IRQ37 */ \ 201 "cspi", /* IRQ38 */ \ 202 "gpt", /* IRQ39 */ \ 203 "epit1", /* IRQ40 */ \ 204 "epit2", /* IRQ41 */ \ 205 "gpio7", /* IRQ42 */ \ 206 "gpio6", /* IRQ43 */ \ 207 "gpio5", /* IRQ44 */ \ 208 "gpio4", /* IRQ45 */ \ 209 "gpio3", /* IRQ46 */ \ 210 "gpio2", /* IRQ47 */ \ 211 "gpio1", /* IRQ48 */ \ 212 "gpio0", /* IRQ49 */ \ 213 "gpio1_low", /* IRQ50 */ \ 214 "gpio1_high", /* IRQ51 */ \ 215 "gpio2_low", /* IRQ52 */ \ 216 "gpio2_high", /* IRQ53 */ \ 217 "gpio3_low", /* IRQ54 */ \ 218 "gpio3_high", /* IRQ55 */ \ 219 "gpio4_low", /* IRQ56 */ \ 220 "gpio4_high", /* IRQ57 */ \ 221 "wdog1", /* IRQ58 */ \ 222 "wdog2", /* IRQ59 */ \ 223 "kpp", /* IRQ60 */ \ 224 "pwm1", /* IRQ61 */ \ 225 "i2c1", /* IRQ62 */ \ 226 "i2c2", /* IRQ63 */ \ 227 "hs_i2c", /* IRQ64 */ \ 228 "rsvd65", /* IRQ65 */ \ 229 "rsvd66", /* IRQ66 */ \ 230 "sim1", /* IRQ67 */ \ 231 "sim2", /* IRQ68 */ \ 232 "iim", /* IRQ69 */ \ 233 "pata", /* IRQ70 */ \ 234 "ccm1", /* IRQ71 */ \ 235 "ccm2", /* IRQ72 */ \ 236 "gpc1", /* IRQ73 */ \ 237 "gpc2", /* IRQ74 */ \ 238 "src", /* IRQ75 */ \ 239 "neon", /* IRQ76 */ \ 240 "perfunit", /* IRQ77 */ \ 241 "cti", /* IRQ78 */ \ 242 "debug1", /* IRQ79 */ \ 243 "debug1", /* IRQ80 */ \ 244 "gpu2d", /* IRQ84 */ \ 245 "gpu2d_busy", /* IRQ85 */ \ 246 "rsvd86", /* IRQ86 */ \ 247 "fec", /* IRQ87 */ \ 248 "owire", /* IRQ88 */ \ 249 "debug2", /* IRQ89 */ \ 250 "sjc", /* IRQ90 */ \ 251 "spdif", /* IRQ91 */ \ 252 "tve", /* IRQ92 */ \ 253 "firi", /* IRQ93 */ \ 254 "pwm2", /* IRQ94 */ \ 255 "slimbus_e", /* IRQ95 */ \ 256 "ssi3", /* IRQ96 */ \ 257 "emi_boot", /* IRQ97 */ \ 258 "debug3", /* IRQ98 */ \ 259 "rxsmc", /* IRQ99 */ \ 260 "vpu_idle", /* IRQ100 */ \ 261 "emi_nfc", /* IRQ101 */ \ 262 "gpu3d_idle", /* IRQ102 */ \ 263 "rsvd103", /* IRQ103 */ \ 264 "rsvd104", /* IRQ104 */ \ 265 "rsvd105", /* IRQ105 */ \ 266 "rsvd106", /* IRQ106 */ \ 267 "rsvd107", /* IRQ107 */ \ 268 "rsvd108", /* IRQ108 */ \ 269 "rsvd109", /* IRQ109 */ \ 270 "rsvd110", /* IRQ110 */ \ 271 "rsvd111", /* IRQ111 */ \ 272 "rsvd112", /* IRQ112 */ \ 273 "rsvd113", /* IRQ113 */ \ 274 "rsvd114", /* IRQ114 */ \ 275 "rsvd115", /* IRQ115 */ \ 276 "rsvd116", /* IRQ116 */ \ 277 "rsvd117", /* IRQ117 */ \ 278 "rsvd118", /* IRQ118 */ \ 279 "rsvd119", /* IRQ119 */ \ 280 "rsvd120", /* IRQ120 */ \ 281 "rsvd121", /* IRQ121 */ \ 282 "rsvd122", /* IRQ122 */ \ 283 "rsvd123", /* IRQ123 */ \ 284 "rsvd124", /* IRQ124 */ \ 285 "rsvd125", /* IRQ125 */ \ 286 "rsvd126", /* IRQ126 */ \ 287 "rsvd127" /* IRQ127 */ \ 288 } 289 290 #define PIC_MAXSOURCES 128 291 #define PIC_MAXMAXSOURCES (PIC_MAXSOURCES+128) 292 293 #include <arm/pic/picvar.h> 294 295 const char *intr_typename(int); 296 297 void imx51_irq_handler(void *); 298 299 #endif /* !_LOCORE */ 300 301 #endif /* _ARM_IMX_IMX51_INTR_H_ */ 302