1 /* $Id: imx23_powerreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_POWERREG_H_ 33 #define _ARM_IMX_IMX23_POWERREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_POWER_BASE 0x80044000 38 #define HW_POWER_SIZE 0x2000 39 40 /* 41 * Power Control Register. 42 */ 43 #define HW_POWER_CTRL 0x000 44 #define HW_POWER_CTRL_SET 0x004 45 #define HW_POWER_CTRL_CLR 0x008 46 #define HW_POWER_CTRL_TOG 0x00c 47 48 #define HW_POWER_CTRL_RSRVD3 __BIT(31) 49 #define HW_POWER_CTRL_CLKGATE __BIT(30) 50 #define HW_POWER_CTRL_RSRVD2 __BITS(29, 28) 51 #define HW_POWER_CTRL_PSWITCH_MID_TRAN __BIT(27) 52 #define HW_POWER_CTRL_RSRVD1 __BITS(26, 25) 53 #define HW_POWER_CTRL_DCDC4P2_BO_IRQ __BIT(24) 54 #define HW_POWER_CTRL_ENIRQ_DCDC4P2_BO __BIT(23) 55 #define HW_POWER_CTRL_VDD5V_DROOP_IRQ __BIT(22) 56 #define HW_POWER_CTRL_ENIRQ_VDD5V_DROOP __BIT(21) 57 #define HW_POWER_CTRL_PSWITCH_IRQ __BIT(20) 58 #define HW_POWER_CTRL_PSWITCH_IRQ_SRC __BIT(19) 59 #define HW_POWER_CTRL_POLARITY_PSWITCH __BIT(18) 60 #define HW_POWER_CTRL_ENIRQ_PSWITCH __BIT(17) 61 #define HW_POWER_CTRL_POLARITY_DC_OK __BIT(16) 62 #define HW_POWER_CTRL_DC_OK_IRQ __BIT(15) 63 #define HW_POWER_CTRL_ENIRQ_DC_OK __BIT(14) 64 #define HW_POWER_CTRL_BATT_BO_IRQ __BIT(13) 65 #define HW_POWER_CTRL_ENIRQBATT_BO __BIT(12) 66 #define HW_POWER_CTRL_VDDIO_BO_IRQ __BIT(11) 67 #define HW_POWER_CTRL_ENIRQ_VDDIO_BO __BIT(10) 68 #define HW_POWER_CTRL_VDDA_BO_IRQ __BIT(9) 69 #define HW_POWER_CTRL_ENIRQ_VDDA_BO __BIT(8) 70 #define HW_POWER_CTRL_VDDD_BO_IRQ __BIT(7) 71 #define HW_POWER_CTRL_ENIRQ_VDDD_BO __BIT(6) 72 #define HW_POWER_CTRL_POLARITY_VBUSVALID __BIT(5) 73 #define HW_POWER_CTRL_VBUSVALID_IRQ __BIT(4) 74 #define HW_POWER_CTRL_ENIRQ_VBUS_VALID __BIT(3) 75 #define HW_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO __BIT(2) 76 #define HW_POWER_CTRL_VDD5V_GT_VDDIO_IRQ __BIT(1) 77 #define HW_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO __BIT(0) 78 79 /* 80 * DC-DC 5V Control Register. 81 */ 82 #define HW_POWER_5VCTRL 0x010 83 #define HW_POWER_5VCTRL_SET 0x014 84 #define HW_POWER_5VCTRL_CLR 0x018 85 #define HW_POWER_5VCTRL_TOG 0x01C 86 87 #define HW_POWER_5VCTRL_RSRVD6 __BITS(31, 30) 88 #define HW_POWER_5VCTRL_VBUSDROOP_TRSH __BITS(29, 28) 89 #define HW_POWER_5VCTRL_RSRVD5 __BIT(27) 90 #define HW_POWER_5VCTRL_HEADROOM_ADJ __BITS(26, 24) 91 #define HW_POWER_5VCTRL_RSRVD4 __BITS(23, 21) 92 #define HW_POWER_5VCTRL_PWD_CHARGE_4P2 __BIT(20) 93 #define HW_POWER_5VCTRL_RSRVD3 __BITS(19, 18) 94 #define HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT __BITS(17, 12) 95 #define HW_POWER_5VCTRL_RSRVD2 __BIT(11) 96 #define HW_POWER_5VCTRL_VBUSVALID_TRSH __BITS(10, 8) 97 #define HW_POWER_5VCTRL_PWDN_5VBRNOUT __BIT(7) 98 #define HW_POWER_5VCTRL_ENABLE_LINREG_ILIMIT __BIT(6) 99 #define HW_POWER_5VCTRL_DCDC_XFER __BIT(5) 100 #define HW_POWER_5VCTRL_VBUSVALID_5VDETECT __BIT(4) 101 #define HW_POWER_5VCTRL_VBUSVALID_TO_B __BIT(3) 102 #define HW_POWER_5VCTRL_ILIMIT_EQ_ZERO __BIT(2) 103 #define HW_POWER_5VCTRL_PWRUP_VBUS_CMPS __BIT(1) 104 #define HW_POWER_5VCTRL_ENABLE_DCDC __BIT(0) 105 106 /* 107 * DC-DC Minimum Power and Miscellaneous Control Register. 108 */ 109 #define HW_POWER_MINPWR 0x020 110 #define HW_POWER_MINPWR_SET 0x024 111 #define HW_POWER_MINPWR_CLR 0x028 112 #define HW_POWER_MINPWR_TOG 0x02C 113 114 #define HW_POWER_MINPWR_RSRVD1 __BITS(31, 15) 115 #define HW_POWER_MINPWR_LOWPWR_4P2 __BIT(14) 116 #define HW_POWER_MINPWR_VDAC_DUMP_CTRL __BIT(13) 117 #define HW_POWER_MINPWR_PWD_BO __BIT(12) 118 #define HW_POWER_MINPWR_USE_VDDXTAL_VBG __BIT(11) 119 #define HW_POWER_MINPWR_PWD_ANA_CMPS __BIT(10) 120 #define HW_POWER_MINPWR_ENABLE_OSC __BIT(9) 121 #define HW_POWER_MINPWR_SELECT_OSC __BIT(8) 122 #define HW_POWER_MINPWR_VBG_OFF __BIT(7) 123 #define HW_POWER_MINPWR_DOUBLE_FETS __BIT(6) 124 #define HW_POWER_MINPWR_HALF_FETS __BIT(5) 125 #define HW_POWER_MINPWR_LESSANA_I __BIT(4) 126 #define HW_POWER_MINPWR_PWD_XTAL24 __BIT(3) 127 #define HW_POWER_MINPWR_DC_STOPCLK __BIT(2) 128 #define HW_POWER_MINPWR_EN_DC_PFM __BIT(1) 129 #define HW_POWER_MINPWR_DC_HALFCLK __BIT(0) 130 131 /* 132 * Battery Charge Control Register. 133 */ 134 #define HW_POWER_CHARGE 0x030 135 #define HW_POWER_CHARGE_SET 0x034 136 #define HW_POWER_CHARGE_CLR 0x038 137 #define HW_POWER_CHARGE_TOG 0x03C 138 139 #define HW_POWER_CHARGE_RSVD5 __BITS(31, 27) 140 #define HW_POWER_CHARGE_ADJ_VOLT __BITS(26, 24) 141 #define HW_POWER_CHARGE_RSRVD3 __BIT(23) 142 #define HW_POWER_CHARGE_ENABLE_LOAD __BIT(22) 143 #define HW_POWER_CHARGE_ENABLE_CHARGER_RESISTORS __BIT(21) 144 #define HW_POWER_CHARGE_ENABLE_FAULT_DETECT __BIT(20) 145 #define HW_POWER_CHARGE_CHRG_STS_OFF __BIT(19) 146 #define HW_POWER_CHARGE_RSVD4 __BIT(18) 147 #define HW_POWER_CHARGE_RSVD3 __BIT(17) 148 #define HW_POWER_CHARGE_PWD_BATTCHRG __BIT(16) 149 #define HW_POWER_CHARGE_RSVD2 __BITS(15, 12) 150 #define HW_POWER_CHARGE_STOP_ILIMIT __BITS(11, 8) 151 #define HW_POWER_CHARGE_RSVD1 __BITS(7, 6) 152 #define HW_POWER_CHARGE_BATTCHRG_I __BITS(5, 0) 153 154 /* 155 * VDDD Supply Targets and Brownouts Control Register. 156 */ 157 #define HW_POWER_VDDDCTRL 0x040 158 159 #define HW_POWER_VDDDCTRL_ADJTN __BITS(31, 28) 160 #define HW_POWER_VDDDCTRL_RSRVD4 __BITS(27, 24) 161 #define HW_POWER_VDDDCTRL_PWDN_BRNOUT __BIT(23) 162 #define HW_POWER_VDDDCTRL_DISABLE_STEPPING __BIT(22) 163 #define HW_POWER_VDDDCTRL_ENABLE_LINREG __BIT(21) 164 #define HW_POWER_VDDDCTRL_DISABLE_FET __BIT(20) 165 #define HW_POWER_VDDDCTRL_RSRVD3 __BITS(19, 18) 166 #define HW_POWER_VDDDCTRL_LINREG_OFFSET __BITS(17, 16) 167 #define HW_POWER_VDDDCTRL_RSRVD2 __BITS(15, 11) 168 #define HW_POWER_VDDDCTRL_BO_OFFSET __BITS(10, 8) 169 #define HW_POWER_VDDDCTRL_RSRVD1 __BITS(7, 5) 170 #define HW_POWER_VDDDCTRL_TRG __BITS(4, 0) 171 172 /* 173 * VDDA Supply Targets and Brownouts Control Register. 174 */ 175 176 #define HW_POWER_VDDACTRL 0x050 177 178 #define HW_POWER_VDDACTRL_RSRVD4 __BITS(31, 20) 179 #define HW_POWER_VDDACTRL_PWDN_BRNOUT __BIT(19) 180 #define HW_POWER_VDDACTRL_DISABLE_STEPPING __BIT(18) 181 #define HW_POWER_VDDACTRL_ENABLE_LINREG __BIT(17) 182 #define HW_POWER_VDDACTRL_DISABLE_FET __BIT(16) 183 #define HW_POWER_VDDACTRL_RSRVD3 __BITS(15, 14) 184 #define HW_POWER_VDDACTRL_LINREG_OFFSET __BITS(13, 12) 185 #define HW_POWER_VDDACTRL_RSRVD2 __BIT(11) 186 #define HW_POWER_VDDACTRL_BO_OFFSET __BITS(10, 8) 187 #define HW_POWER_VDDACTRL_RSRVD1 __BITS(7, 5) 188 #define HW_POWER_VDDACTRL_TRG __BITS(4, 0) 189 190 /* 191 * VDDIO Supply Targets and Brownouts Control Register. 192 */ 193 #define HW_POWER_VDDIOCTRL 0x060 194 195 #define HW_POWER_VDDIOCTRL_RSRVD5 __BITS(31, 24) 196 #define HW_POWER_VDDIOCTRL_ADJTN __BITS(23, 20) 197 #define HW_POWER_VDDIOCTRL_RSRVD4 __BIT(19) 198 #define HW_POWER_VDDIOCTRL_PWDN_BRNOUT __BIT(18) 199 #define HW_POWER_VDDIOCTRL_DISABLE_STEPPING __BIT(17) 200 #define HW_POWER_VDDIOCTRL_DISABLE_FET __BIT(16) 201 #define HW_POWER_VDDIOCTRL_RSRVD3 __BITS(15, 14) 202 #define HW_POWER_VDDIOCTRL_LINREG_OFFSET __BITS(13, 12) 203 #define HW_POWER_VDDIOCTRL_RSRVD2 __BIT(11) 204 #define HW_POWER_VDDIOCTRL_BO_OFFSET __BITS(10, 8) 205 #define HW_POWER_VDDIOCTRL_RSRVD1 __BITS(7, 5) 206 #define HW_POWER_VDDIOCTRL_TRG __BITS(4, 0) 207 208 /* 209 * VDDMEM Supply Targets Control Register. 210 */ 211 #define HW_POWER_VDDMEMCTRL 0x070 212 213 #define HW_POWER_VDDMEMCTRL_RSRVD2 __BITS(31, 11) 214 #define HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE __BIT(10) 215 #define HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT __BIT(9) 216 #define HW_POWER_VDDMEMCTRL_ENABLE_LINREG __BIT(8) 217 #define HW_POWER_VDDMEMCTRL_RSRVD1 __BITS(7, 5) 218 #define HW_POWER_VDDMEMCTRL_TRG __BITS(4, 0) 219 220 /* 221 * DC-DC Converter 4.2V Control Register. 222 */ 223 #define HW_POWER_DCDC4P2 0x080 224 225 #define HW_POWER_DCDC4P2_DROPOUT_CTRL __BITS(31, 28) 226 #define HW_POWER_DCDC4P2_RSRVD5 __BITS(27, 26) 227 #define HW_POWER_DCDC4P2_ISTEAL_THRESH __BITS(25, 24) 228 #define HW_POWER_DCDC4P2_ENABLE_4P2 __BIT(23) 229 #define HW_POWER_DCDC4P2_ENABLE_DCDC __BIT(22) 230 #define HW_POWER_DCDC4P2_HYST_DIR __BIT(21) 231 #define HW_POWER_DCDC4P2_HYST_THRESH __BIT(20) 232 #define HW_POWER_DCDC4P2_RSRVD3 __BIT(19) 233 #define HW_POWER_DCDC4P2_TRG __BITS(18, 16) 234 #define HW_POWER_DCDC4P2_RSRVD2 __BITS(15, 13) 235 #define HW_POWER_DCDC4P2_BO __BITS(12, 8) 236 #define HW_POWER_DCDC4P2_RSRVD1 __BITS(7, 5) 237 #define HW_POWER_DCDC4P2_CMPTRIP __BITS(4, 0) 238 239 /* 240 * DC-DC Miscellaneous Register. 241 */ 242 #define HW_POWER_MISC 0x090 243 244 #define HW_POWER_MISC_RSRVD2 __BITS(31, 7) 245 #define HW_POWER_MISC_FREQSEL __BITS(6, 4) 246 #define HW_POWER_MISC_RSRVD1 __BIT(3) 247 #define HW_POWER_MISC_DELAY_TIMING __BIT(2) 248 #define HW_POWER_MISC_TEST __BIT(1) 249 #define HW_POWER_MISC_SEL_PLLCLK __BIT(0) 250 251 /* 252 * DC-DC Duty Cycle Limits Control Register. 253 */ 254 #define HW_POWER_DCLIMITS 0x0A0 255 256 #define HW_POWER_DCLIMITS_RSRVD3 __BITS(31, 16) 257 #define HW_POWER_DCLIMITS_RSRVD2 __BIT(15) 258 #define HW_POWER_DCLIMITS_POSLIMIT_BUCK __BITS(14, 8) 259 #define HW_POWER_DCLIMITS_RSRVD1 __BIT(7) 260 #define HW_POWER_DCLIMITS_NEGLIMIT __BITS(6, 0) 261 262 /* 263 * Converter Loop Behavior Control Register. 264 */ 265 #define HW_POWER_LOOPCTRL 0x0B0 266 #define HW_POWER_LOOPCTRL_SET 0x0B4 267 #define HW_POWER_LOOPCTRL_CLR 0x0B8 268 #define HW_POWER_LOOPCTRL_TOG 0x0BC 269 270 #define HW_POWER_LOOPCTRL_RSRVD3 __BITS(31, 21) 271 #define HW_POWER_LOOPCTRL_TOGGLE_DIF __BIT(20) 272 #define HW_POWER_LOOPCTRL_HYST_SIGN __BIT(19) 273 #define HW_POWER_LOOPCTRL_EN_CM_HYST __BIT(18) 274 #define HW_POWER_LOOPCTRL_EN_DF_HYST __BIT(17) 275 #define HW_POWER_LOOPCTRL_CM_HYST_THRESH __BIT(16) 276 #define HW_POWER_LOOPCTRL_DF_HYST_THRESH __BIT(15) 277 #define HW_POWER_LOOPCTRL_RCSCALE_THRESH __BIT(14) 278 #define HW_POWER_LOOPCTRL_EN_RCSCALE __BITS(13, 12) 279 #define HW_POWER_LOOPCTRL_RSRVD2 __BIT(11) 280 #define HW_POWER_LOOPCTRL_DC_FF __BITS(10, 8) 281 #define HW_POWER_LOOPCTRL_DC_R __BITS(7, 4) 282 #define HW_POWER_LOOPCTRL_RSRVD1 __BITS(3, 2) 283 #define HW_POWER_LOOPCTRL_DC_C __BITS(1, 0) 284 285 /* 286 * Power Subsystem Status Register. 287 */ 288 #define HW_POWER_STS 0x0C0 289 290 #define HW_POWER_STS_RSVD4 __BITS(31, 30) 291 #define HW_POWER_STS_PWRUP_SOURCE __BITS(29, 24) 292 #define HW_POWER_STS_RSVD3 __BITS(23, 22) 293 #define HW_POWER_STS_PSWITCH __BITS(21, 20) 294 #define HW_POWER_STS_RSVD2 __BITS(19, 18) 295 #define HW_POWER_STS_AVALID_STATUS __BIT(17) 296 #define HW_POWER_STS_BVALID_STATUS __BIT(16) 297 #define HW_POWER_STS_VBUSVALID_STATUS __BIT(15) 298 #define HW_POWER_STS_SESSEND_STATUS __BIT(14) 299 #define HW_POWER_STS_BATT_BO __BIT(13) 300 #define HW_POWER_STS_VDD5V_FAULT __BIT(12) 301 #define HW_POWER_STS_CHRGSTS __BIT(11) 302 #define HW_POWER_STS_DCDC_4P2_BO __BIT(10) 303 #define HW_POWER_STS_RSVD1 __BIT(9) 304 #define HW_POWER_STS_VDDIO_BO __BIT(8) 305 #define HW_POWER_STS_VDDA_BO __BIT(7) 306 #define HW_POWER_STS_VDDD_BO __BIT(6) 307 #define HW_POWER_STS_VDD5V_GT_VDDIO __BIT(5) 308 #define HW_POWER_STS_VDD5V_DROOP __BIT(4) 309 #define HW_POWER_STS_AVALID __BIT(3) 310 #define HW_POWER_STS_BVALID __BIT(2) 311 #define HW_POWER_STS_VBUSVALID __BIT(1) 312 #define HW_POWER_STS_SESSEND __BIT(0) 313 314 /* 315 * Transistor Speed Control and Status Register. 316 */ 317 #define HW_POWER_SPEED 0x0D0 318 #define HW_POWER_SPEED_SET 0x0D4 319 #define HW_POWER_SPEED_CLR 0x0D8 320 #define HW_POWER_SPEED_TOG 0x0DC 321 322 #define HW_POWER_SPEED_RSRVD1 __BITS(31, 24) 323 #define HW_POWER_SPEED_STATUS __BITS(23, 16) 324 #define HW_POWER_SPEED_RSRVD0 __BITS(15, 2) 325 #define HW_POWER_SPEED_CTRL __BITS(1, 0) 326 327 /* 328 * Battery Level Monitor Register. 329 */ 330 #define HW_POWER_BATTMONITOR 0x0E0 331 332 #define HW_POWER_BATTMONITOR_RSRVD3 __BITS(31, 26) 333 #define HW_POWER_BATTMONITOR_BATT_VAL __BITS(25, 16) 334 #define HW_POWER_BATTMONITOR_RSRVD2 __BITS(15, 11) 335 #define HW_POWER_BATTMONITOR_EN_BATADJ __BIT(10) 336 #define HW_POWER_BATTMONITOR_PWDN_BATTBRNOUT __BIT(9) 337 #define HW_POWER_BATTMONITOR_BRWNOUT_PWD __BIT(8) 338 #define HW_POWER_BATTMONITOR_RSRVD1 __BITS(7, 5) 339 #define HW_POWER_BATTMONITOR_BRWNOUT_LVL __BITS(4, 0) 340 341 /* 342 * Power Module Reset Register. 343 */ 344 #define HW_POWER_RESET 0x100 345 #define HW_POWER_RESET_SET 0x104 346 #define HW_POWER_RESET_CLR 0x108 347 #define HW_POWER_RESET_TOG 0x10C 348 349 #define HW_POWER_RESET_UNLOCK __BITS(31, 16) 350 #define HW_POWER_RESET_RSRVD1 __BITS(15, 2) 351 #define HW_POWER_RESET_PWD_OFF __BIT(1) 352 #define HW_POWER_RESET_PWD __BIT(0) 353 354 /* 355 * Power Module Debug Register. 356 */ 357 #define HW_POWER_DEBUG 0x110 358 #define HW_POWER_DEBUG_SET 0x114 359 #define HW_POWER_DEBUG_CLR 0x118 360 #define HW_POWER_DEBUG_TOG 0x11C 361 362 #define HW_POWER_DEBUG_RSRVD0 __BITS(31, 4) 363 #define HW_POWER_DEBUG_VBUSVALIDPIOLOCK __BIT(3) 364 #define HW_POWER_DEBUG_AVALIDPIOLOCK __BIT(2) 365 #define HW_POWER_DEBUG_BVALIDPIOLOCK __BIT(1) 366 #define HW_POWER_DEBUG_SESSENDPIOLOCK __BIT(0) 367 368 /* 369 * Power Module Special Register. 370 */ 371 #define HW_POWER_SPECIAL 0x120 372 #define HW_POWER_SPECIAL_SET 0x124 373 #define HW_POWER_SPECIAL_CLR 0x128 374 #define HW_POWER_SPECIAL_TOG 0x12C 375 376 #define HW_POWER_SPECIAL_TEST __BITS(31, 0) 377 378 /* 379 * Power Module Version Register. 380 */ 381 #define HW_POWER_VERSION 0x130 382 383 #define HW_POWER_VERSION_MAJOR __BITS(31, 24) 384 #define HW_POWER_VERSION_MINOR __BITS(23, 16) 385 #define HW_POWER_VERSION_STEP __BITS(15, 0) 386 387 #endif /* !_ARM_IMX_IMX23_POWERREG_H_ */ 388