1 /* $NetBSD: footbridge.c,v 1.26 2012/10/10 21:53:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge.c,v 1.26 2012/10/10 21:53:09 skrll Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/conf.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 #include <uvm/uvm_extern.h> 47 48 #include <dev/pci/pcivar.h> 49 #define _ARM32_BUS_DMA_PRIVATE 50 #include <sys/bus.h> 51 #include <machine/intr.h> 52 #include <machine/bootconfig.h> 53 54 #include <arm/cpuconf.h> 55 #include <arm/cpufunc.h> 56 57 #include <arm/footbridge/footbridgevar.h> 58 #include <arm/footbridge/dc21285reg.h> 59 #include <arm/footbridge/dc21285mem.h> 60 #include <arm/footbridge/footbridge.h> 61 62 /* 63 * DC21285 'Footbridge' device 64 * 65 * This probes and attaches the footbridge device 66 * It then configures any children 67 */ 68 69 /* Declare prototypes */ 70 71 static int footbridge_match(device_t parent, cfdata_t cf, void *aux); 72 static void footbridge_attach(device_t parent, device_t self, void *aux); 73 static int footbridge_print(void *aux, const char *pnp); 74 static int footbridge_intr(void *arg); 75 76 /* Driver and attach structures */ 77 CFATTACH_DECL_NEW(footbridge, sizeof(struct footbridge_softc), 78 footbridge_match, footbridge_attach, NULL, NULL); 79 80 /* Various bus space tags */ 81 extern struct bus_space footbridge_bs_tag; 82 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie); 83 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie); 84 struct bus_space footbridge_csr_tag; 85 struct bus_space footbridge_pci_io_bs_tag; 86 struct bus_space footbridge_pci_mem_bs_tag; 87 extern struct arm32_pci_chipset footbridge_pci_chipset; 88 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag; 89 extern struct arm32_dma_range footbridge_dma_ranges[1]; 90 91 /* Used in footbridge_clock.c */ 92 struct footbridge_softc *clock_sc; 93 94 /* Set to non-zero to enable verbose reporting of footbridge system ints */ 95 int footbridge_intr_report = 0; 96 97 int footbridge_found; 98 99 void 100 footbridge_pci_bs_tag_init(void) 101 { 102 /* Set up the PCI bus tags */ 103 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 104 (void *)DC21285_PCI_IO_VBASE); 105 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 106 (void *)DC21285_PCI_MEM_BASE); 107 } 108 109 /* 110 * int footbridge_print(void *aux, const char *name) 111 * 112 * print configuration info for children 113 */ 114 115 static int 116 footbridge_print(void *aux, const char *pnp) 117 { 118 union footbridge_attach_args *fba = aux; 119 120 if (pnp) 121 aprint_normal("%s at %s", fba->fba_name, pnp); 122 return(UNCONF); 123 } 124 125 /* 126 * int footbridge_match(device_t parent, cfdata_t cf, void *aux) 127 * 128 * Just return ok for this if it is device 0 129 */ 130 131 static int 132 footbridge_match(device_t parent, cfdata_t cf, void *aux) 133 { 134 if (footbridge_found) 135 return(0); 136 return(1); 137 } 138 139 140 /* 141 * void footbridge_attach(device_t parent, device_t dev, void *aux) 142 * 143 */ 144 145 static void 146 footbridge_attach(device_t parent, device_t self, void *aux) 147 { 148 struct footbridge_softc *sc = device_private(self); 149 union footbridge_attach_args fba; 150 int vendor, device, rev; 151 152 /* There can only be 1 footbridge. */ 153 footbridge_found = 1; 154 155 clock_sc = sc; 156 157 sc->sc_dev = self; 158 sc->sc_iot = &footbridge_bs_tag; 159 160 /* Map the Footbridge */ 161 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE, 162 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh)) 163 panic("%s: Cannot map registers", device_xname(self)); 164 165 /* Read the ID to make sure it is what we think it is */ 166 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID); 167 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID); 168 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION); 169 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID) 170 panic("%s: Unrecognised ID", device_xname(self)); 171 172 aprint_normal(": DC21285 rev %d\n", rev); 173 174 /* Disable all interrupts from the footbridge */ 175 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff); 176 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff); 177 178 /* Install a generic handler to catch a load of system interrupts */ 179 sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH, 180 "serr", footbridge_intr, sc); 181 sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH, 182 "sdram parity", footbridge_intr, sc); 183 sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH, 184 "data parity", footbridge_intr, sc); 185 sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH, 186 "mast abt", footbridge_intr, sc); 187 sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH, 188 "targ abt", footbridge_intr, sc); 189 sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH, 190 "parity", footbridge_intr, sc); 191 192 /* Set up the PCI bus tags */ 193 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 194 (void *)DC21285_PCI_IO_VBASE); 195 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 196 (void *)DC21285_PCI_MEM_BASE); 197 198 /* calibrate the delay loop */ 199 calibrate_delay(); 200 201 /* 202 * It seems that the default of the memory being visible from 0 upwards 203 * on the PCI bus causes issues when DMAing from traditional PC VGA 204 * address. This breaks dumping core on cats, as DMAing pages in the 205 * range 0xb800-0xc000 cause the system to hang. This suggests that 206 * the VGA BIOS is taking over those addresses. 207 * (note that the range 0xb800-c000 is on an S3 card, others may vary 208 * 209 * To workaround this the SDRAM window on the PCI bus is shifted 210 * to 0x20000000, and the DMA range setup to match. 211 */ 212 { 213 /* first calculate the correct base address mask */ 214 int memory_size = bootconfig.dram[0].pages * PAGE_SIZE; 215 uint32_t mask; 216 217 /* window has to be at least 256KB, and up to 256MB */ 218 for (mask = 0x00040000; mask < 0x10000000; mask <<= 1) 219 if (mask >= memory_size) 220 break; 221 mask--; 222 mask &= SDRAM_MASK_256MB; 223 224 /* 225 * configure the mask, the offset into SDRAM and the address 226 * SDRAM is exposed on the PCI bus. 227 */ 228 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_MASK, mask); 229 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_OFFSET, 0); 230 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_MEMORY_ADDR, 0x20000000); 231 232 /* configure the dma range for the footbridge to match */ 233 footbridge_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 234 footbridge_dma_ranges[0].dr_busbase = 0x20000000; 235 footbridge_dma_ranges[0].dr_len = memory_size; 236 } 237 238 /* Attach the PCI bus */ 239 fba.fba_pba.pba_pc = &footbridge_pci_chipset; 240 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag; 241 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag; 242 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag; 243 fba.fba_pba.pba_dmat64 = NULL; 244 fba.fba_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 245 fba.fba_pba.pba_bus = 0; 246 fba.fba_pba.pba_bridgetag = NULL; 247 config_found_ia(self, "pcibus", &fba.fba_pba, pcibusprint); 248 249 /* Attach uart device */ 250 fba.fba_fca.fca_name = "fcom"; 251 fba.fba_fca.fca_iot = sc->sc_iot; 252 fba.fba_fca.fca_ioh = sc->sc_ioh; 253 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX; 254 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX; 255 config_found_ia(self, "footbridge", &fba.fba_fca, footbridge_print); 256 257 /* Setup fast SA110 cache clean area */ 258 #ifdef CPU_SA110 259 if (cputype == CPU_ID_SA110) 260 footbridge_sa110_cc_setup(); 261 #endif /* CPU_SA110 */ 262 263 } 264 265 /* Generic footbridge interrupt handler */ 266 267 int 268 footbridge_intr(void *arg) 269 { 270 struct footbridge_softc *sc = arg; 271 u_int ctrl, intr; 272 273 /* 274 * Read the footbridge control register and check for 275 * SERR and parity errors 276 */ 277 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL); 278 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR | 279 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR); 280 if (intr) { 281 /* Report the interrupt if reporting is enabled */ 282 if (footbridge_intr_report) 283 printf("footbridge_intr: ctrl=%08x\n", intr); 284 /* Clear the interrupt state */ 285 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL, 286 ctrl | intr); 287 } 288 /* 289 * Read the PCI status register and check for errors 290 */ 291 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG); 292 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT 293 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR 294 | PCI_STATUS_PARITY_DETECT); 295 if (intr) { 296 /* Report the interrupt if reporting is enabled */ 297 if (footbridge_intr_report) 298 printf("footbridge_intr: pcistat=%08x\n", intr); 299 /* Clear the interrupt state */ 300 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 301 PCI_COMMAND_STATUS_REG, ctrl | intr); 302 } 303 return(0); 304 } 305 306 /* End of footbridge.c */ 307