1 /* $NetBSD: footbridge.c,v 1.30 2022/09/27 06:36:41 skrll Exp $ */
2
3 /*
4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997,1998 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Mark Brinicombe
19 * for the NetBSD Project.
20 * 4. The name of the company nor the name of the author may be used to
21 * endorse or promote products derived from this software without specific
22 * prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: footbridge.c,v 1.30 2022/09/27 06:36:41 skrll Exp $");
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/conf.h>
44 #include <sys/device.h>
45 #include <uvm/uvm_extern.h>
46
47 #include <dev/pci/pcivar.h>
48 #define _ARM32_BUS_DMA_PRIVATE
49 #include <sys/bus.h>
50 #include <machine/intr.h>
51 #include <machine/bootconfig.h>
52
53 #include <arm/cpuconf.h>
54 #include <arm/cpufunc.h>
55
56 #include <arm/footbridge/footbridgevar.h>
57 #include <arm/footbridge/dc21285reg.h>
58 #include <arm/footbridge/dc21285mem.h>
59 #include <arm/footbridge/footbridge.h>
60
61 /*
62 * DC21285 'Footbridge' device
63 *
64 * This probes and attaches the footbridge device
65 * It then configures any children
66 */
67
68 /* Declare prototypes */
69
70 static int footbridge_match(device_t parent, cfdata_t cf, void *aux);
71 static void footbridge_attach(device_t parent, device_t self, void *aux);
72 static int footbridge_print(void *aux, const char *pnp);
73 static int footbridge_intr(void *arg);
74
75 /* Driver and attach structures */
76 CFATTACH_DECL_NEW(footbridge, sizeof(struct footbridge_softc),
77 footbridge_match, footbridge_attach, NULL, NULL);
78
79 /* Various bus space tags */
80 extern struct bus_space footbridge_bs_tag;
81 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie);
82 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie);
83 struct bus_space footbridge_csr_tag;
84 struct bus_space footbridge_pci_io_bs_tag;
85 struct bus_space footbridge_pci_mem_bs_tag;
86 extern struct arm32_pci_chipset footbridge_pci_chipset;
87 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag;
88 extern struct arm32_dma_range footbridge_dma_ranges[1];
89
90 /* Used in footbridge_clock.c */
91 struct footbridge_softc *clock_sc;
92
93 /* Set to non-zero to enable verbose reporting of footbridge system ints */
94 int footbridge_intr_report = 0;
95
96 int footbridge_found;
97
98 void
footbridge_pci_bs_tag_init(void)99 footbridge_pci_bs_tag_init(void)
100 {
101 /* Set up the PCI bus tags */
102 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
103 (void *)DC21285_PCI_IO_VBASE);
104 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
105 (void *)DC21285_PCI_MEM_BASE);
106 }
107
108 /*
109 * int footbridge_print(void *aux, const char *name)
110 *
111 * print configuration info for children
112 */
113
114 static int
footbridge_print(void * aux,const char * pnp)115 footbridge_print(void *aux, const char *pnp)
116 {
117 union footbridge_attach_args *fba = aux;
118
119 if (pnp)
120 aprint_normal("%s at %s", fba->fba_name, pnp);
121 return(UNCONF);
122 }
123
124 /*
125 * int footbridge_match(device_t parent, cfdata_t cf, void *aux)
126 *
127 * Just return ok for this if it is device 0
128 */
129
130 static int
footbridge_match(device_t parent,cfdata_t cf,void * aux)131 footbridge_match(device_t parent, cfdata_t cf, void *aux)
132 {
133 if (footbridge_found)
134 return(0);
135 return(1);
136 }
137
138
139 /*
140 * void footbridge_attach(device_t parent, device_t dev, void *aux)
141 *
142 */
143
144 static void
footbridge_attach(device_t parent,device_t self,void * aux)145 footbridge_attach(device_t parent, device_t self, void *aux)
146 {
147 struct footbridge_softc *sc = device_private(self);
148 union footbridge_attach_args fba;
149 int vendor, device, rev;
150
151 /* There can only be 1 footbridge. */
152 footbridge_found = 1;
153
154 clock_sc = sc;
155
156 sc->sc_dev = self;
157 sc->sc_iot = &footbridge_bs_tag;
158
159 /* Map the Footbridge */
160 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE,
161 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh))
162 panic("%s: Cannot map registers", device_xname(self));
163
164 /* Read the ID to make sure it is what we think it is */
165 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID);
166 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID);
167 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION);
168 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID)
169 panic("%s: Unrecognised ID", device_xname(self));
170
171 aprint_normal(": DC21285 rev %d\n", rev);
172
173 /* Disable all interrupts from the footbridge */
174 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff);
175 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff);
176
177 /* Install a generic handler to catch a load of system interrupts */
178 sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH,
179 "serr", footbridge_intr, sc);
180 sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH,
181 "sdram parity", footbridge_intr, sc);
182 sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH,
183 "data parity", footbridge_intr, sc);
184 sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH,
185 "mast abt", footbridge_intr, sc);
186 sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH,
187 "targ abt", footbridge_intr, sc);
188 sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH,
189 "parity", footbridge_intr, sc);
190
191 /* Set up the PCI bus tags */
192 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
193 (void *)DC21285_PCI_IO_VBASE);
194 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
195 (void *)DC21285_PCI_MEM_BASE);
196
197 /* calibrate the delay loop */
198 calibrate_delay();
199
200 /*
201 * It seems that the default of the memory being visible from 0 upwards
202 * on the PCI bus causes issues when DMAing from traditional PC VGA
203 * address. This breaks dumping core on cats, as DMAing pages in the
204 * range 0xb800-0xc000 cause the system to hang. This suggests that
205 * the VGA BIOS is taking over those addresses.
206 * (note that the range 0xb800-c000 is on an S3 card, others may vary
207 *
208 * To workaround this the SDRAM window on the PCI bus is shifted
209 * to 0x20000000, and the DMA range setup to match.
210 */
211 {
212 /* first calculate the correct base address mask */
213 int memory_size = bootconfig.dram[0].pages * PAGE_SIZE;
214 uint32_t mask;
215
216 /* window has to be at least 256KB, and up to 256MB */
217 for (mask = 0x00040000; mask < 0x10000000; mask <<= 1)
218 if (mask >= memory_size)
219 break;
220 mask--;
221 mask &= SDRAM_MASK_256MB;
222
223 /*
224 * configure the mask, the offset into SDRAM and the address
225 * SDRAM is exposed on the PCI bus.
226 */
227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_MASK, mask);
228 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_OFFSET, 0);
229 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_MEMORY_ADDR, 0x20000000);
230
231 /* configure the dma range for the footbridge to match */
232 footbridge_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address;
233 footbridge_dma_ranges[0].dr_busbase = 0x20000000;
234 footbridge_dma_ranges[0].dr_len = memory_size;
235 }
236
237 /* Attach the PCI bus */
238 fba.fba_pba.pba_pc = &footbridge_pci_chipset;
239 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag;
240 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag;
241 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag;
242 fba.fba_pba.pba_dmat64 = NULL;
243 fba.fba_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
244 fba.fba_pba.pba_bus = 0;
245 fba.fba_pba.pba_bridgetag = NULL;
246 config_found(self, &fba.fba_pba, pcibusprint,
247 CFARGS(.iattr = "pcibus"));
248
249 /* Attach uart device */
250 fba.fba_fca.fca_name = "fcom";
251 fba.fba_fca.fca_iot = sc->sc_iot;
252 fba.fba_fca.fca_ioh = sc->sc_ioh;
253 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX;
254 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX;
255 config_found(self, &fba.fba_fca, footbridge_print,
256 CFARGS(.iattr = "footbridge"));
257
258 /* Setup fast SA110 cache clean area */
259 #ifdef CPU_SA110
260 if (cputype == CPU_ID_SA110)
261 footbridge_sa110_cc_setup();
262 #endif /* CPU_SA110 */
263
264 }
265
266 /* Generic footbridge interrupt handler */
267
268 int
footbridge_intr(void * arg)269 footbridge_intr(void *arg)
270 {
271 struct footbridge_softc *sc = arg;
272 u_int ctrl, intr;
273
274 /*
275 * Read the footbridge control register and check for
276 * SERR and parity errors
277 */
278 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL);
279 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR |
280 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR);
281 if (intr) {
282 /* Report the interrupt if reporting is enabled */
283 if (footbridge_intr_report)
284 printf("footbridge_intr: ctrl=%08x\n", intr);
285 /* Clear the interrupt state */
286 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL,
287 ctrl | intr);
288 }
289 /*
290 * Read the PCI status register and check for errors
291 */
292 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG);
293 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT
294 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR
295 | PCI_STATUS_PARITY_DETECT);
296 if (intr) {
297 /* Report the interrupt if reporting is enabled */
298 if (footbridge_intr_report)
299 printf("footbridge_intr: pcistat=%08x\n", intr);
300 /* Clear the interrupt state */
301 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
302 PCI_COMMAND_STATUS_REG, ctrl | intr);
303 }
304 return(0);
305 }
306
307 /* End of footbridge.c */
308