1 /* $NetBSD: mesongxbb_clkc.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: mesongxbb_clkc.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/amlogic/meson_clk.h>
41 #include <arm/amlogic/mesongxbb_clkc.h>
42
43 #define CBUS_REG(x) ((x) << 2)
44
45 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
46 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
47 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
48 #define HHI_GCLK_OTHER CBUS_REG(0x54)
49 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
50 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
51 #define HHI_NAND_CLK_CNTL CBUS_REG(0x97)
52 #define HHI_SD_EMMC_CLK_CNTL CBUS_REG(0x99)
53 #define HHI_MPLL_CNTL CBUS_REG(0xa0)
54 #define HHI_MPLL_CNTL2 CBUS_REG(0xa1)
55 #define HHI_MPLL_CNTL5 CBUS_REG(0xa4)
56 #define HHI_MPLL_CNTL6 CBUS_REG(0xa5)
57 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6)
58 #define HHI_MPLL_CNTL8 CBUS_REG(0xa7)
59 #define HHI_MPLL_CNTL9 CBUS_REG(0xa8)
60 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0)
61 #define HHI_SYS_PLL_CNTL_LOCK __BIT(31)
62 #define HHI_SYS_PLL_CNTL_OD __BITS(17,16)
63 #define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)
64 #define HHI_SYS_PLL_CNTL_MUL __BITS(8,0)
65
66 static int mesongxbb_clkc_match(device_t, cfdata_t, void *);
67 static void mesongxbb_clkc_attach(device_t, device_t, void *);
68
69 struct mesongxbb_clkc_config {
70 const char *name;
71 };
72
73 static const struct mesongxbb_clkc_config gxbb_config = {
74 .name = "Meson GXBB",
75 };
76
77 static const struct mesongxbb_clkc_config gxl_config = {
78 .name = "Meson GXL",
79 };
80
81 static const struct device_compatible_entry compat_data[] = {
82 { .compat = "amlogic,gxbb-clkc", .data = &gxbb_config },
83 { .compat = "amlogic,gxl-clkc", .data = &gxl_config },
84 DEVICE_COMPAT_EOL
85 };
86
87 CFATTACH_DECL_NEW(mesongxbb_clkc, sizeof(struct meson_clk_softc),
88 mesongxbb_clkc_match, mesongxbb_clkc_attach, NULL, NULL);
89
90 static const char *mpeg_sel_parents[] = { "xtal", NULL, "fclk_div7", "mpll1", "mpll2", "fclk_div4", "fclk_div3", "fclk_div5" };
91 static const char *sd_emmc_clk0_sel_parents[] = { "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7" };
92
93 static struct meson_clk_clk mesongxbb_clkc_clks[] = {
94
95 MESON_CLK_PLL(MESONGXBB_CLOCK_SYS_PLL_DCO, "pll_sys_dco", "xtal",
96 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
97 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
98 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
99 MESON_CLK_PLL_REG_INVALID, /* frac */
100 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
101 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
102 0),
103
104 MESON_CLK_DIV(MESONGXBB_CLOCK_SYS_PLL, "sys_pll", "pll_sys_dco",
105 HHI_SYS_PLL_CNTL, /* reg */
106 __BITS(17,16), /* div */
107 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT),
108
109 MESON_CLK_PLL(MESONGXBB_CLOCK_FIXED_PLL_DCO, "pll_fixed_dco", "xtal",
110 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
111 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
112 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
113 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
114 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
115 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
116 0),
117
118 MESON_CLK_DIV(MESONGXBB_CLOCK_FIXED_PLL, "pll_fixed", "pll_fixed_dco",
119 HHI_MPLL_CNTL, /* reg */
120 __BITS(17,16), /* div */
121 MESON_CLK_DIV_POWER_OF_TWO),
122
123 MESON_CLK_DIV(MESONGXBB_CLOCK_MPLL_PREDIV, "mpll_prediv", "pll_fixed",
124 HHI_MPLL_CNTL5, /* reg */
125 __BIT(12), /* div */
126 0),
127
128 MESON_CLK_MPLL(MESONGXBB_CLOCK_MPLL0_DIV, "mpll0_div", "mpll_prediv",
129 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
130 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
131 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
132 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
133 0),
134 MESON_CLK_MPLL(MESONGXBB_CLOCK_MPLL1_DIV, "mpll1_div", "mpll_prediv",
135 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
136 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
137 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
138 MESON_CLK_PLL_REG_INVALID, /* ssen */
139 0),
140 MESON_CLK_MPLL(MESONGXBB_CLOCK_MPLL2_DIV, "mpll2_div", "mpll_prediv",
141 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
142 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
143 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
144 MESON_CLK_PLL_REG_INVALID, /* ssen */
145 0),
146
147 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
148 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
149 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
150
151 MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1),
152 MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1),
153 MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1),
154 MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1),
155 MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1),
156
157 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
158 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
159 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
160 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
161 MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
162 MESON_CLK_MUX(MESONGXBB_CLOCK_MPEG_SEL, "mpeg_sel", mpeg_sel_parents,
163 HHI_MPEG_CLK_CNTL, /* reg */
164 __BITS(14,12), /* sel */
165 0),
166
167 MESON_CLK_DIV(MESONGXBB_CLOCK_MPEG_DIV, "mpeg_div", "mpeg_sel",
168 HHI_MPEG_CLK_CNTL, /* reg */
169 __BITS(6,0), /* div */
170 0),
171
172 MESON_CLK_MUX(MESONGXBB_CLOCK_SD_EMMC_A_CLK0_SEL, "sd_emmc_a_clk0_sel", sd_emmc_clk0_sel_parents,
173 HHI_SD_EMMC_CLK_CNTL, /* reg */
174 __BITS(11,9), /* sel */
175 0),
176 MESON_CLK_MUX(MESONGXBB_CLOCK_SD_EMMC_B_CLK0_SEL, "sd_emmc_b_clk0_sel", sd_emmc_clk0_sel_parents,
177 HHI_SD_EMMC_CLK_CNTL, /* reg */
178 __BITS(27,25), /* sel */
179 0),
180 MESON_CLK_MUX(MESONGXBB_CLOCK_SD_EMMC_C_CLK0_SEL, "sd_emmc_c_clk0_sel", sd_emmc_clk0_sel_parents,
181 HHI_NAND_CLK_CNTL, /* reg */
182 __BITS(11,9), /* sel */
183 0),
184
185 MESON_CLK_DIV(MESONGXBB_CLOCK_SD_EMMC_A_CLK0_DIV, "sd_emmc_a_clk0_div", "sd_emmc_a_clk0_sel",
186 HHI_SD_EMMC_CLK_CNTL, /* reg */
187 __BITS(6,0), /* div */
188 0),
189 MESON_CLK_DIV(MESONGXBB_CLOCK_SD_EMMC_B_CLK0_DIV, "sd_emmc_b_clk0_div", "sd_emmc_b_clk0_sel",
190 HHI_SD_EMMC_CLK_CNTL, /* reg */
191 __BITS(22,16), /* div */
192 0),
193 MESON_CLK_DIV(MESONGXBB_CLOCK_SD_EMMC_C_CLK0_DIV, "sd_emmc_c_clk0_div", "sd_emmc_c_clk0_sel",
194 HHI_NAND_CLK_CNTL, /* reg */
195 __BITS(6,0), /* div */
196 0),
197
198 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", "sd_emmc_a_clk0_div", HHI_SD_EMMC_CLK_CNTL, 7),
199 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0", "sd_emmc_b_clk0_div", HHI_SD_EMMC_CLK_CNTL, 23),
200 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C_CLK0, "sd_emmc_c_clk0", "sd_emmc_c_clk0_div", HHI_NAND_CLK_CNTL, 7),
201
202 MESON_CLK_GATE(MESONGXBB_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
203
204 MESON_CLK_GATE(MESONGXBB_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
205 MESON_CLK_GATE(MESONGXBB_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
206 MESON_CLK_GATE(MESONGXBB_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
207 MESON_CLK_GATE(MESONGXBB_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
208 MESON_CLK_GATE(MESONGXBB_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
209 MESON_CLK_GATE(MESONGXBB_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
210 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A, "sd_emmc_a", "clk81", HHI_GCLK_MPEG0, 24),
211 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B, "sd_emmc_b", "clk81", HHI_GCLK_MPEG0, 25),
212 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C, "sd_emmc_c", "clk81", HHI_GCLK_MPEG0, 26),
213
214 MESON_CLK_GATE(MESONGXBB_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3),
215 MESON_CLK_GATE(MESONGXBB_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16),
216 MESON_CLK_GATE(MESONGXBB_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21),
217 MESON_CLK_GATE(MESONGXBB_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22),
218 MESON_CLK_GATE(MESONGXBB_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26),
219 MESON_CLK_GATE(MESONGXBB_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30),
220
221 MESON_CLK_GATE(MESONGXBB_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
222 MESON_CLK_GATE(MESONGXBB_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
223 MESON_CLK_GATE(MESONGXBB_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),
224 };
225
226 static int
mesongxbb_clkc_match(device_t parent,cfdata_t cf,void * aux)227 mesongxbb_clkc_match(device_t parent, cfdata_t cf, void *aux)
228 {
229 struct fdt_attach_args * const faa = aux;
230
231 return of_compatible_match(faa->faa_phandle, compat_data);
232 }
233
234 static void
mesongxbb_clkc_attach(device_t parent,device_t self,void * aux)235 mesongxbb_clkc_attach(device_t parent, device_t self, void *aux)
236 {
237 struct meson_clk_softc * const sc = device_private(self);
238 struct fdt_attach_args * const faa = aux;
239 const struct mesongxbb_clkc_config *conf;
240 const int phandle = faa->faa_phandle;
241
242 sc->sc_dev = self;
243 sc->sc_phandle = faa->faa_phandle;
244 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
245 if (sc->sc_syscon == NULL) {
246 aprint_error(": couldn't get syscon registers\n");
247 return;
248 }
249
250 sc->sc_clks = mesongxbb_clkc_clks;
251 sc->sc_nclks = __arraycount(mesongxbb_clkc_clks);
252
253 meson_clk_attach(sc);
254
255 conf = of_compatible_lookup(phandle, compat_data)->data;
256
257 aprint_naive("\n");
258 aprint_normal(": %s clock controller\n", conf->name);
259
260 meson_clk_print(sc);
261 }
262