xref: /netbsd-src/sys/arch/alpha/pci/tsp_pci.c (revision f446c320287b5da434e360fd5a037baf7d611379)
1 /* $NetBSD: tsp_pci.c,v 1.12 2021/06/25 03:45:59 thorpej Exp $ */
2 
3 /*-
4  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Ross Harvey.
17  * 4. The name of Ross Harvey may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 
35 __KERNEL_RCSID(0, "$NetBSD: tsp_pci.c,v 1.12 2021/06/25 03:45:59 thorpej Exp $");
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/device.h>
41 
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 
45 #include <machine/autoconf.h>
46 #include <machine/rpb.h>
47 
48 #include <alpha/pci/tsreg.h>
49 #include <alpha/pci/tsvar.h>
50 
51 #define tsp_pci() { Generate ctags(1) key. }
52 
53 static pcireg_t	tsp_conf_read(void *, pcitag_t, int);
54 static void	tsp_conf_write(void *, pcitag_t, int, pcireg_t);
55 
56 void
tsp_pci_init(pci_chipset_tag_t pc,void * v)57 tsp_pci_init(pci_chipset_tag_t pc, void *v)
58 {
59 	pc->pc_conf_v = v;
60 	pc->pc_conf_read = tsp_conf_read;
61 	pc->pc_conf_write = tsp_conf_write;
62 }
63 
64 /*
65  * Tsunami makes this a lot easier than it used to be, automatically
66  * generating type 0 or type 1 cycles, and quietly returning -1 with
67  * no errors on unanswered probes.
68  */
69 static pcireg_t
tsp_conf_read(void * cpv,pcitag_t tag,int offset)70 tsp_conf_read(void *cpv, pcitag_t tag, int offset)
71 {
72 	pcireg_t *datap, data;
73 	struct tsp_config *pcp = cpv;
74 
75 	if ((unsigned int)offset >= PCI_CONF_SIZE)
76 		return (pcireg_t) -1;
77 
78 	datap = S_PAGE(pcp->pc_iobase | P_PCI_CONFIG | tag | (offset & ~3));
79 	alpha_mb();
80 	data = *datap;
81 	alpha_mb();
82 	return data;
83 }
84 
85 static void
tsp_conf_write(void * cpv,pcitag_t tag,int offset,pcireg_t data)86 tsp_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
87 {
88 	pcireg_t *datap;
89 	struct tsp_config *pcp = cpv;
90 
91 	if ((unsigned int)offset >= PCI_CONF_SIZE)
92 		return;
93 
94 	datap = S_PAGE(pcp->pc_iobase | P_PCI_CONFIG | tag | (offset & ~3));
95 	alpha_mb();
96 	*datap = data;
97 	alpha_mb();
98 }
99 
100 #define NTH_STR(n, ...) ((const char *[]){ __VA_ARGS__ }[n])
101 
102 void
tsp_print_error(unsigned int indent,unsigned long p_error)103 tsp_print_error(unsigned int indent, unsigned long p_error)
104 {
105 	char buf[40];
106 
107 	if (PER_INV(p_error)) {
108 		IPRINTF(indent, "data invalid\n");
109 		return;
110 	}
111 
112 	if (!PER_ERR(p_error))
113 		return;
114 
115 	snprintb(buf, 40,
116 		 "\177\20"
117 		 "b\0Error lost\0"
118 		 "b\1PCI SERR#\0"
119 		 "b\2PCI PERR#\0"
120 		 "b\3Delayed completion retry timeout\0"
121 		 "b\4Invalid S/G page table entry\0"
122 		 "b\5Address parity error\0"
123 		 "b\6Target abort\0"
124 		 "b\7PCI read data parity error\0"
125 		 "b\10no PCI DEVSEL#\0"
126 		 "b\11unknown\0"
127 		 "b\12Uncorrectable ECC\0"
128 		 "b\13Correctable ECC\0",
129 		 PER_ERR(p_error));
130 	IPRINTF(indent, "error    = %s\n", buf);
131 
132 	if (PER_ECC(p_error)) {
133 		IPRINTF(indent, "address  = 0x%09lx\n", PER_SADR(p_error));
134 		IPRINTF(indent, "command  = 0x%lx<%s>\n", PER_CMD(p_error),
135 			NTH_STR(PER_CMD(p_error) & 0x3,
136 				"DMA read", "DMA RMW", "?", "S/G read"));
137 		IPRINTF(indent, "syndrome = 0x%02lx\n", PER_SYN(p_error));
138 	} else {
139 		IPRINTF(indent, "address  = 0x%08lx, 0x%lx<%s>\n",
140 			PER_PADR(p_error), PER_TRNS(p_error),
141 			NTH_STR(PER_TRNS(p_error), "No DAC", "DAC SG Win3",
142 				"Monster Window", "Monster Window"));
143 		IPRINTF(indent, "command  = 0x%lx<%s>\n", PER_CMD(p_error),
144 			NTH_STR(PER_CMD(p_error),
145 				"PCI IACK", "PCI special cycle",
146 				"PCI I/O read", "PCI I/O write", "?",
147 				"PCI PTP write", "PCI memory read",
148 				"PCI memory write", "PCI CSR write",
149 				"?", "?", "?", "?", "?", "?", "?"));
150 	}
151 }
152