1 /* $NetBSD: mcpcia_pci.c,v 1.13 2021/05/07 16:58:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: mcpcia_pci.c,v 1.13 2021/05/07 16:58:34 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <alpha/pci/mcpciareg.h> 45 #include <alpha/pci/mcpciavar.h> 46 47 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 48 49 static void mcpcia_attach_hook(device_t, device_t, 50 struct pcibus_attach_args *); 51 static int mcpcia_bus_maxdevs(void *, int); 52 static pcitag_t mcpcia_make_tag(void *, int, int, int); 53 static void mcpcia_decompose_tag(void *, pcitag_t, int *, int *, int *); 54 static pcireg_t mcpcia_conf_read(void *, pcitag_t, int); 55 static void mcpcia_conf_write(void *, pcitag_t, int, pcireg_t); 56 57 void 58 mcpcia_pci_init(pci_chipset_tag_t pc, void *v) 59 { 60 pc->pc_conf_v = v; 61 pc->pc_attach_hook = mcpcia_attach_hook; 62 pc->pc_bus_maxdevs = mcpcia_bus_maxdevs; 63 pc->pc_make_tag = mcpcia_make_tag; 64 pc->pc_decompose_tag = mcpcia_decompose_tag; 65 pc->pc_conf_read = mcpcia_conf_read; 66 pc->pc_conf_write = mcpcia_conf_write; 67 } 68 69 static void 70 mcpcia_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 71 { 72 } 73 74 static int 75 mcpcia_bus_maxdevs(void *cpv, int busno) 76 { 77 return (MCPCIA_MAXDEV); 78 } 79 80 static pcitag_t 81 mcpcia_make_tag(void *cpv, int b, int d, int f) 82 { 83 pcitag_t tag; 84 tag = (b << 21) | (d << 16) | (f << 13); 85 return (tag); 86 } 87 88 static void 89 mcpcia_decompose_tag(void *cpv, pcitag_t tag, int *bp, int *dp, int *fp) 90 { 91 if (bp != NULL) 92 *bp = (tag >> 21) & 0xff; 93 if (dp != NULL) 94 *dp = (tag >> 16) & 0x1f; 95 if (fp != NULL) 96 *fp = (tag >> 13) & 0x7; 97 } 98 99 static pcireg_t 100 mcpcia_conf_read(void *cpv, pcitag_t tag, int offset) 101 { 102 struct mcpcia_config *ccp = cpv; 103 pcireg_t *dp, data = (pcireg_t) -1; 104 unsigned long paddr; 105 106 if ((unsigned int)offset >= PCI_CONF_SIZE) 107 return (data); 108 109 /* 110 * There's nothing in slot 0 on a primary bus- don't even try. 111 */ 112 if ((tag >> 21) == 0 && ((uint32_t) tag & 0x1f0000) == 0) 113 return (data); 114 115 if (ccp == NULL) { 116 panic("NULL ccp in mcpcia_conf_read"); 117 } 118 paddr = (unsigned long) tag; 119 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 120 paddr |= ((unsigned long) ((offset >> 2) << 7)); 121 paddr |= MCPCIA_PCI_CONF; 122 paddr |= ccp->cc_sysbase; 123 dp = (pcireg_t *)KV(paddr); 124 if (badaddr(dp, sizeof (*dp)) == 0) { 125 data = *dp; 126 } 127 return (data); 128 } 129 130 static void 131 mcpcia_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 132 { 133 struct mcpcia_config *ccp = cpv; 134 pcireg_t *dp; 135 unsigned long paddr; 136 137 if ((unsigned int)offset >= PCI_CONF_SIZE) 138 return; 139 140 /* 141 * There's nothing in slot 0 on a primary bus- don't even try. 142 */ 143 if ((tag >> 21) == 0 && ((uint32_t) tag & 0x1f0000) == 0) 144 return; 145 146 if (ccp == NULL) { 147 panic("NULL ccp in mcpcia_conf_write"); 148 } 149 paddr = (unsigned long) tag; 150 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */ 151 paddr |= ((unsigned long) ((offset >> 2) << 7)); 152 paddr |= MCPCIA_PCI_CONF; 153 paddr |= ccp->cc_sysbase; 154 155 dp = (pcireg_t *)KV(paddr); 156 *dp = data; 157 } 158