1 /* $NetBSD: mcpcia_pci.c,v 1.14 2021/06/25 03:46:54 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1998 by Matthew Jacob
5 * NASA AMES Research Center.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice immediately at the beginning of the file, without modification,
13 * this list of conditions, and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
34
35 __KERNEL_RCSID(0, "$NetBSD: mcpcia_pci.c,v 1.14 2021/06/25 03:46:54 thorpej Exp $");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <alpha/pci/mcpciareg.h>
45 #include <alpha/pci/mcpciavar.h>
46
47 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
48
49 static int mcpcia_bus_maxdevs(void *, int);
50 static pcitag_t mcpcia_make_tag(void *, int, int, int);
51 static void mcpcia_decompose_tag(void *, pcitag_t, int *, int *, int *);
52 static pcireg_t mcpcia_conf_read(void *, pcitag_t, int);
53 static void mcpcia_conf_write(void *, pcitag_t, int, pcireg_t);
54
55 void
mcpcia_pci_init(pci_chipset_tag_t pc,void * v)56 mcpcia_pci_init(pci_chipset_tag_t pc, void *v)
57 {
58 pc->pc_conf_v = v;
59 pc->pc_bus_maxdevs = mcpcia_bus_maxdevs;
60 pc->pc_make_tag = mcpcia_make_tag;
61 pc->pc_decompose_tag = mcpcia_decompose_tag;
62 pc->pc_conf_read = mcpcia_conf_read;
63 pc->pc_conf_write = mcpcia_conf_write;
64 }
65
66 static int
mcpcia_bus_maxdevs(void * cpv,int busno)67 mcpcia_bus_maxdevs(void *cpv, int busno)
68 {
69 return (MCPCIA_MAXDEV);
70 }
71
72 static pcitag_t
mcpcia_make_tag(void * cpv,int b,int d,int f)73 mcpcia_make_tag(void *cpv, int b, int d, int f)
74 {
75 pcitag_t tag;
76 tag = (b << 21) | (d << 16) | (f << 13);
77 return (tag);
78 }
79
80 static void
mcpcia_decompose_tag(void * cpv,pcitag_t tag,int * bp,int * dp,int * fp)81 mcpcia_decompose_tag(void *cpv, pcitag_t tag, int *bp, int *dp, int *fp)
82 {
83 if (bp != NULL)
84 *bp = (tag >> 21) & 0xff;
85 if (dp != NULL)
86 *dp = (tag >> 16) & 0x1f;
87 if (fp != NULL)
88 *fp = (tag >> 13) & 0x7;
89 }
90
91 static pcireg_t
mcpcia_conf_read(void * cpv,pcitag_t tag,int offset)92 mcpcia_conf_read(void *cpv, pcitag_t tag, int offset)
93 {
94 struct mcpcia_config *ccp = cpv;
95 pcireg_t *dp, data = (pcireg_t) -1;
96 unsigned long paddr;
97
98 if ((unsigned int)offset >= PCI_CONF_SIZE)
99 return (data);
100
101 /*
102 * There's nothing in slot 0 on a primary bus- don't even try.
103 */
104 if ((tag >> 21) == 0 && ((uint32_t) tag & 0x1f0000) == 0)
105 return (data);
106
107 if (ccp == NULL) {
108 panic("NULL ccp in mcpcia_conf_read");
109 }
110 paddr = (unsigned long) tag;
111 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */
112 paddr |= ((unsigned long) ((offset >> 2) << 7));
113 paddr |= MCPCIA_PCI_CONF;
114 paddr |= ccp->cc_sysbase;
115 dp = (pcireg_t *)KV(paddr);
116 if (badaddr(dp, sizeof (*dp)) == 0) {
117 data = *dp;
118 }
119 return (data);
120 }
121
122 static void
mcpcia_conf_write(void * cpv,pcitag_t tag,int offset,pcireg_t data)123 mcpcia_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
124 {
125 struct mcpcia_config *ccp = cpv;
126 pcireg_t *dp;
127 unsigned long paddr;
128
129 if ((unsigned int)offset >= PCI_CONF_SIZE)
130 return;
131
132 /*
133 * There's nothing in slot 0 on a primary bus- don't even try.
134 */
135 if ((tag >> 21) == 0 && ((uint32_t) tag & 0x1f0000) == 0)
136 return;
137
138 if (ccp == NULL) {
139 panic("NULL ccp in mcpcia_conf_write");
140 }
141 paddr = (unsigned long) tag;
142 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */
143 paddr |= ((unsigned long) ((offset >> 2) << 7));
144 paddr |= MCPCIA_PCI_CONF;
145 paddr |= ccp->cc_sysbase;
146
147 dp = (pcireg_t *)KV(paddr);
148 *dp = data;
149 }
150