1 /* $NetBSD: rsidereg.h,v 1.2 2005/12/11 12:16:05 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Chris Gilbert 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Thanks to Gareth Simpson, Simtec Electronics for providing 31 * the hardware information. 32 */ 33 34 /* 35 * Registers and address offsets for the Simtec IDE card. 36 */ 37 38 /* IDE drive registers */ 39 40 #define PRIMARY_DRIVE_REGISTERS_POFFSET 0x0302b800 41 #define PRIMARY_AUX_REGISTER_POFFSET (PRIMARY_DRIVE_REGISTERS_POFFSET + 0x380) 42 43 #define SECONDARY_DRIVE_REGISTERS_POFFSET 0x0302bc00 44 #define SECONDARY_AUX_REGISTER_POFFSET (SECONDARY_DRIVE_REGISTERS_POFFSET + 0x380) 45 46 #define DRIVE_REGISTERS_SPACE (8 * 0x40) 47 #define DRIVE_REGISTER_BYTE_SPACING (0x40) 48 #define DRIVE_REGISTER_SPACING_SHIFT 6 49 50 /* Other registers */ 51 #define CONTROL_SECONDARY_IRQ IRQ_NEVENT1 52 #define CONTROL_PRIMARY_IRQ IRQ_NEVENT2 53