1.\" $NetBSD: ichlpcib.4,v 1.12 2017/02/18 22:39:02 wiz Exp $ 2.\" 3.\" Copyright (c) 2004 The NetBSD Foundation, Inc. 4.\" All rights reserved. 5.\" 6.\" This code is derived from software contributed to The NetBSD Foundation 7.\" by Minoura Makoto and Matthew R. Green. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28.\" POSSIBILITY OF SUCH DAMAGE. 29.\" 30.Dd February 17, 2017 31.Dt ICHLPCIB 4 x86 32.Os 33.Sh NAME 34.Nm ichlpcib 35.Nd Intel ICH LPC Interface Bridge 36.Sh SYNOPSIS 37.Cd "ichlpcib* at pci? dev ? function ?" 38.Cd "fwhrng* at ichlpcib?" 39.Cd "hpet0 at ichlpcib?" 40.Cd "isa0 at ichlpcib?" 41.Cd "gpio* at ichlpcib?" 42.Cd "tco* at ichlpcib?" 43.Sh DESCRIPTION 44The 45.Nm 46driver supports the Intel ICH LPC Interface Bridges on compatible 47chipsets. 48Supported functions include: 49.Bl -bullet 50.It 51Watchdog timer. 52The watchdog timer may be configured for a 1 seconds (on ICH6 or newer) 53and 2 seconds (on ICH5 or older) min period and for a 23 seconds 54(on ICH5 or older) or 367 seconds max period (on ICH6 or newer). 55.Pp 56Prior to 57.Nx 8.0 , 58the 59.Xr x86/tco 4 60watchdog timer was included as part of the 61.Nm 62driver, and did not require explicit configuration. 63.It 64Power Management timer. 65A 24-bit timer available to be used by the timecounters framework. 66.It 67SpeedStep. 68In some older systems the SpeedStep function is also available, and can be 69used to switch between high and low frequency (to reduce power consumption) 70via the 71.Li machdep.speedstep_state 72.Xr sysctl 8 73node. 74A value of 0 will use the low frequency (low power) and a 1 will 75enable the high frequency (full power). 76.It 77General Purpose Input/Output. 78The ICH provides up to 64 I/O pins which can be accessed through the 79.Xr gpio 4 80framework. 81.El 82.Sh SEE ALSO 83.Xr gpio 4 , 84.Xr x86/est 4 , 85.Xr x86/fwhrng 4 , 86.Xr x86/hpet 4 , 87.Xr x86/ioapic 4 , 88.Xr x86/tco 4 , 89.Xr sysctl 8 , 90.Xr wdogctl 8 91.Rs 92.%A Intel Corporation 93.%T Intel I/O Controller Hub 6 (ICH6) Family 94.%D January, 2005 95.%U http://www.intel.com/assets/pdf/datasheet/301473.pdf 96.Re 97.Rs 98.%A Intel Corporation 99.%T Intel I/O Controller Hub 7 (ICH7) Family 100.%D April, 2007 101.%U http://www.intel.com/Assets/PDF/datasheet/307013.pdf 102.Re 103.Rs 104.%A Intel Corporation 105.%T Intel I/O Controller Hub 8 (ICH8) Family 106.%D May, 2007 107.%U http://www.intel.com/assets/pdf/datasheet/313056.pdf 108.Re 109.Rs 110.%A Intel Corporation 111.%T Using the Intel ICH Family Watchdog Timer (WDT) 112.%D September, 2002 113.%U ftp://download.intel.com/design/chipsets/applnots/29227301.pdf 114.Re 115.Sh HISTORY 116The 117.Nm 118driver first appeared in 119.Nx 3.0 . 120.Sh AUTHORS 121The 122.Nm 123driver was written by 124.An Minoura Makoto 125and 126.An Matthew R. Green . 127