1.\" $NetBSD: gpiopps.4,v 1.4 2023/08/01 20:41:48 andvar Exp $ 2.\" 3.\" Copyright (c) 2016 Brad Spencer <brad@anduin.eldar.org> 4.\" 5.\" Permission to use, copy, modify, and distribute this software for any 6.\" purpose with or without fee is hereby granted, provided that the above 7.\" copyright notice and this permission notice appear in all copies. 8.\" 9.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16.\" 17.Dd May 11, 2018 18.Dt GPIOPPS 4 19.Os 20.Sh NAME 21.Nm gpiopps 22.Nd install a PPS handler on GPIO pins 23.Sh SYNOPSIS 24.Cd "gpiopps* at gpio? offset 0 mask 0x1 flag 0x0" 25.Sh DESCRIPTION 26The 27.Nm 28driver provides a 1PPS handler using the PPSAPI on one or two GPIO pins. 29.Pp 30The base pin number is specified in the kernel configuration file with the 31.Ar offset 32locator. 33The 34.Ar mask 35should have 1 or 2 bits set, indicating which pins offset from the 36base pin should be used 37.Pq 0 .. 31 . 38Pin configurations are discussed below. 39.Pp 40The 41.Ar flag 42locator modifies the pin configuration: 43.Bl -tag -width "XXXXXXXX" 44.It Dv 0x01 45The PPS ASSERT signal should be triggered on the negative 46.Pq falling 47edge of the 48assert pin. 49The default is to trigger on the positive 50.Pq rising 51edge of the pin. 52.It Dv 0x02 53By default, 54.Nm 55will use double-edge triggering when only a single pin is specified 56and the underlying GPIO hardware supports it. 57This flag disables the use of double-edge triggering. 58.El 59.Pp 60If a single pin is specified, 61.Nm 62uses double-edge triggering to support ASSERT and CLEAR PPS signals. 63If the underlying GPIO hardware does not support double-edge triggering, 64or if this feature is disabled in the 65.Ar flag 66locator, then only ASSERT will be signaled on the specified edge. 67.Pp 68If two pins are specified, the first pin is used to trigger the 69ASSERT signal and the second pin is used to trigger the CLEAR 70signal. 71The ASSERT pin's trigger edge is specified by by the 72.Ar flag 73locator, and the CLEAR pin triggers on the opposite edge. 74This allows ASSERT and CLEAR signals to be triggered even if the underlying 75GPIO hardware does not support double-edge triggering. 76In this scenario, both GPIO pins would be connected in parallel to the 77device sending the 1PPS signals. 78.Pp 79The 80.Ar offset , 81.Ar mask , 82and 83.Ar flag 84locators can also be specified when 85.Nm 86is attached at runtime using the 87.Dv GPIOATTACH 88.Xr ioctl 2 89on the 90.Xr gpio 4 91device. 92.Sh SEE ALSO 93.Xr gpio 4 , 94.Xr drvctl 8 , 95.Xr gpioctl 8 96.Sh HISTORY 97The 98.Nm 99driver first appeared in 100.Nx 9.0 . 101.Sh AUTHORS 102.An -nosplit 103The 104.Nm 105driver was written by 106.An Brad Spencer Aq Mt brad@anduin.eldar.org . 107