1.\" $NetBSD: ath.4,v 1.6 2004/10/04 19:12:52 rumble Exp $ 2.\" 3.\" Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 4.\" All rights reserved. 5.\"" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer, 11.\" without modification. 12.\" 2. Redistributions in binary form must reproduce at minimum a disclaimer 13.\" similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14.\" redistribution must be conditioned upon including a substantially 15.\" similar Disclaimer requirement for further binary redistribution. 16.\" 3. Neither the names of the above-listed copyright holders nor the names 17.\" of any contributors may be used to endorse or promote products derived 18.\" from this software without specific prior written permission. 19.\" 20.\" NO WARRANTY 21.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23.\" LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24.\" AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25.\" THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26.\" OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29.\" IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31.\" THE POSSIBILITY OF SUCH DAMAGES. 32.\" 33.\" 34.\" Note: This man page was taken by Perry Metzger almost entirely 35.\" from the "ath" and "ath_hal" man pages in FreeBSD. I claim no 36.\" copyright because there was nearly no original work performed in 37.\" doing so. Maintainers should check the FreeBSD originals for 38.\" updates against the following two revisions and incorporate them 39.\" if needed: 40.\" 41.\" $FreeBSD: /repoman/r/ncvs/src/share/man/man4/ath.4,v 1.16 2004/02/18 08:30:08 maxim Exp $ 42.\" parts from $FreeBSD: /repoman/r/ncvs/src/share/man/man4/ath_hal.4,v 1.7 2004/01/07 20:49:51 blackend Exp $ 43.\" 44.Dd February 27, 2004 45.Dt ATH 4 46.Os 47.Sh NAME 48.Nm ath 49.Nd Atheros IEEE 802.11 driver 50.Sh SYNOPSIS 51.Cd "ath* at pci? dev ? function ?" 52.Cd "ath* at cardbus? dev ? function ?" 53.Sh DESCRIPTION 54The 55.Nm 56driver provides support for wireless network adapters based on 57the Atheros AR5210, AR5211, and AR5212 chips. 58Chip-specific support is provided by the Atheros Hardware Access Layer 59(HAL), which is currently available only in binary form for selected 60architectures. 61.Pp 62Supported features include 802.11 and 802.3 frames, power management, BSS, 63IBSS, and host-based access point operation modes. 64All host/device interaction is via DMA. 65.Pp 66The 67.Nm 68driver encapsulates all IP and ARP traffic as 802.11 frames, however 69it can receive either 802.11 or 802.3 frames. 70Transmit speed and operating mode is selectable 71depending on your hardware. 72.Pp 73AR5210-based devices support 802.11a operation with transmit speeds 74of 6 Mbps, 9 Mbps, 12 Mbps, 18 Mbps, 24 Mbps, 36 Mbps, 48 Mbps, and 54 Mbps. 75.Pp 76AR5211-based devices support 802.11a and 802.11b operation with transmit 77speeds as above for 802.11a operation and 781Mbps, 2Mbps, 5.5 Mbps and 11Mbps for 802.11b operation. 79.Pp 80AR5212-based devices support 802.11a, 802.11b, and 802.11g operation 81with transmit speeds appropriate to each. 82.Pp 83All chips also support an Atheros Turbo Mode (TM) that operates in the 84802.11a frequency range with 2x the transmit speeds. 85(This mode is, however, only interoperable with other Atheros-based devices.) 86.Pp 87The actual transmit speed used is dependent on signal quality and the 88.Dq rate control 89algorithm employed by the driver. 90All chips support WEP encryption. 91AR5211 and AR5212 support the AES, TKIP, and Michael cryptographic 92operations required for WPA but at this time the driver does not support them. 93To enable encryption, use 94.Xr ifconfig 8 . 95.Pp 96By default, the 97.Nm 98driver configures the card for BSS operation (aka infrastructure 99mode). 100This mode requires the use of an access point (base station). 101.Pp 102The 103.Nm 104driver also supports the standard IBSS point-to-point mode 105where stations can communicate amongst themselves without the 106aid of an access point. 107.Pp 108The driver may also be configured to operate in hostap mode. 109In this mode a host may function as an access point (base station). 110Access points are different than operating in IBSS mode. 111They operate in BSS mode. 112They allow for easier roaming and bridge all ethernet traffic such 113that machines connected via an access point appear to be on the local 114ethernet segment. 115.Pp 116For more information on configuring this device, see 117.Xr ifconfig 8 . 118.Pp 119Devices supported by the 120.Nm 121driver come in either CardBus or mini-PCI packages. 122Wireless cards in CardBus slots may be inserted and ejected on the fly. 123.Pp 124The following cards are among those supported by the 125.Nm 126driver: 127.Pp 128.Bl -column -compact "Samsung SWL-5200N" "AR5212" "CardBus" "a/b/g" 129.Em "Card Chip Bus Standard" 130Aztech WL830PC AR5212 CardBus b/g 131D-Link DWL-A650 AR5210 CardBus a 132D-Link DWL-AB650 AR5211 CardBus a/b 133D-Link DWL-A520 AR5210 PCI a 134D-Link DWL-AG520 AR5212 PCI a/b/g 135D-Link DWL-AG650 AR5212 CardBus a/b/g 136D-Link DWL-G520 AR5212 PCI b/g 137D-Link DWL-G650B AR5212 CardBus b/g 138Elecom LD-WL54AG AR5212 CardBus a/b/g 139Elecom LD-WL54 AR5211 CardBus a 140Fujitsu E5454 AR5212 CardBus a/b/g 141Fujitsu FMV-JW481 AR5212 CardBus a/b/g 142Fujitsu E5454 AR5212 CardBus a/b/g 143HP NC4000 AR5212 PCI a/b/g 144I/O Data WN-AB AR5212 CardBus a/b 145I/O Data WN-AG AR5212 CardBus a/b/g 146I/O Data WN-A54 AR5212 CardBus a 147Linksys WMP55AG AR5212 PCI a/b/g 148Linksys WPC51AB AR5211 CardBus a/b 149Linksys WPC55AG AR5212 CardBus a/b/g 150NEC PA-WL/54AG AR5212 CardBus a/b/g 151Netgear WAG311 AR5212 PCI a/b/g 152Netgear WAB501 AR5211 CardBus a/b 153Netgear WAG511 AR5212 CardBus a/b/g 154Netgear WG311 AR5212 PCI b/g 155Netgear WG511T AR5212 CardBus b/g 156Orinoco 8480 AR5212 CardBus a/b/g 157Orinoco 8470WD AR5212 CardBus a/b/g 158Proxim Skyline 4030 AR5210 CardBus a 159Proxim Skyline 4032 AR5210 PCI a 160Samsung SWL-5200N AR5212 CardBus a/b/g 161SMC SMC2735W AR5210 CardBus a 162Sony PCWA-C700 AR5212 CardBus a/b 163Sony PCWA-C300S AR5212 CardBus b/g 164Sony PCWA-C500 AR5210 CardBus a 1653Com 3CRPAG175 AR5212 CardBus a/b/g 166.El 167.Pp 168An up to date list can be found at 169.Pa http://customerproducts.atheros.com/customerproducts . 170.Sh DIAGNOSTICS 171.Bl -diag 172.It "ath%d: unable to attach hardware; HAL status %u" 173The Atheros Hardware Access Layer was unable to configure the hardware 174as requested. 175The status code is explained in the HAL include file 176.Pa contrib/sys/dev/ic/athhal.h . 177.It "ath%d: failed to allocate descriptors: %d" 178The driver was unable to allocate contiguous memory for the transmit 179and receive descriptors. 180This usually indicates system memory is scarce and/or fragmented. 181.It "ath%d: unable to setup a data xmit queue!" 182The request to the HAL to setup the transmit queue for normal 183data frames failed. 184This should not happen. 185.It "ath%d: unable to setup a beacon xmit queue!" 186The request to the HAL to setup the transmit queue for 802.11 beacon frames 187failed. 188This should not happen. 189.It "ath%d: 802.11 address: %s" 190The MAC address programmed in the EEPROM is displayed. 191.It "ath%d: hardware error; resetting" 192An unrecoverable error in the hardware occurred. 193Errors of this sort include unrecoverable DMA errors. 194The driver will reset the hardware and continue. 195.It "ath%d: rx FIFO overrun; resetting" 196The receive FIFO in the hardware overflowed before the data could be 197transferred to the host. 198This typically occurs because the hardware ran short of receive 199descriptors and had no place to transfer received data. 200The driver will reset the hardware and continue. 201.It "ath%d: unable to reset hardware; hal status %u" 202The Atheros Hardware Access Layer was unable to reset the hardware 203as requested. 204The status code is explained in the HAL include file 205.Pa contrib/sys/dev/ic/athhal.h . 206This should not happen. 207.It "ath%d: unable to start recv logic" 208The driver was unable to restart frame reception. 209This should not happen. 210.It "ath%d: device timeout" 211A frame dispatched to the hardware for transmission did not complete in time. 212The driver will reset the hardware and continue. 213This should not happen. 214.It "ath%d: bogus xmit rate 0x%x" 215An invalid transmit rate was specified for an outgoing frame. 216The frame is discarded. 217This should not happen. 218.It "ath%d: ath_chan_set: unable to reset channel %u (%u Mhz)" 219The Atheros Hardware Access Layer was unable to reset the hardware 220when switching channels during scanning. 221This should not happen. 222.It "ath%d: unable to allocate channel table" 223The driver was unable to allocate memory for the table used to hold 224the set of available channels. 225.It "ath%d: unable to collect channel list from hal" 226A problem occurred while querying the HAL to find the set of available 227channels for the device. 228This should not happen. 229.It "ath%d: %s: %dM -\*[Gt] %dM (%d ok, %d err, %d retr)" 230The driver's rate control algorithm changed the current rate for transmitting 231frames. 232This message is temporarily enabled for normal use to help in diagnosing 233and improving the rate control algorithm. 234The message indicates the new and old transmit rates and the statistics 235it used to decide on this change. 236.It "ath%d: failed to enable memory mapping" 237The driver was unable to enable memory-mapped I/O to the PCI device registers. 238This should not happen. 239.It "ath%d: failed to enable bus mastering" 240The driver was unable to enable the device as a PCI bus master for doing DMA. 241This should not happen. 242.It "ath%d: cannot map register space" 243The driver was unable to map the device registers into the host address space. 244This should not happen. 245.It "ath%d: could not map interrupt" 246The driver was unable to allocate an IRQ for the device interrupt. 247This should not happen. 248.It "ath%d: could not establish interrupt" 249The driver was unable to install the device interrupt handler. 250This should not happen. 251.El 252.Sh SEE ALSO 253.Xr arp 4 , 254.Xr cardbus 4 , 255.Xr ifmedia 4 , 256.Xr netintro 4 , 257.Xr pci 4 , 258.Xr ifconfig 8 259.Sh HISTORY 260The 261.Nm 262device driver first appeared in 263.Fx 5.2 . 264It was ported to 265.Nx 2.0 . 266.Sh AUTHORS 267The 268.Nm 269driver was originally written by 270.An Sam Leffler , 271and was ported to 272.Nx 273by 274.An David Young . 275.Sh CAVEATS 276Different regulatory domains have different default channels for adhoc 277mode. 278See 279.Xr ifconfig 8 280for information on how to change the channel. 281Different regulatory domains may not be able to communicate with each 282other with 802.11a as different regulatory domains do not necessarily 283have overlapping channels. 284.Pp 285Revision A1 of the D-LINK DWL-G520 and DWL-G650 are based on an 286Intersil PrismGT chip and are not supported by this driver. 287.Pp 288The HAL module is constructed from a binary component and 289operating system-dependent source code. 290Redistribution and use in source and binary forms, without 291modification, are permitted provided that the conditions 292set forth in 293.Pa src/contrib/sys/dev/ic/athhal-COPYRIGHT 294are observed. 295.Sh BUGS 296Performance in lossy environments is suboptimal. 297The algorithm used to select the rate for transmitted packets is 298very simplistic. 299There is no software retransmit; only hardware retransmit is used. 300Contributors are encouraged to replace the existing rate control algorithm 301with a better one (hint: all the information needed is available to the driver). 302.Pp 303The driver does not fully enable power-save operation of the chip; 304consequently power use is suboptimal. 305