1# sh testcase for pshl <imm> 2# mach: shdsp 3# as(shdsp): -defsym sim_cpu=1 -dsp 4 5 .include "testutils.inc" 6 7 start 8 9pshl_imm: ! shift logical, immediate operand 10 set_grs_a5a5 11 lds r0, a0 12 pcopy a0, a1 13 lds r0, x0 14 lds r0, x1 15 lds r0, y0 16 lds r0, y1 17 pcopy x0, m0 18 pcopy y1, m1 19 20 set_sreg 0x10000, a0 21 pshl #0, a0 22 assert_sreg 0x10000, a0 23 pshl #-0, a0 24 assert_sreg 0x10000, a0 25 26 pshl #1, a0 27 assert_sreg 0x20000, a0 28 pshl #-1, a0 29 assert_sreg 0x10000, a0 30 31 pshl #2, a0 32 assert_sreg 0x40000, a0 33 pshl #-2, a0 34 assert_sreg 0x10000, a0 35 36 pshl #3, a0 37 assert_sreg 0x80000, a0 38 pshl #-3, a0 39 assert_sreg 0x10000, a0 40 41 pshl #4, a0 42 assert_sreg 0x100000, a0 43 pshl #-4, a0 44 assert_sreg 0x10000, a0 45 46 pshl #5, a0 47 assert_sreg 0x200000, a0 48 pshl #-5, a0 49 assert_sreg 0x10000, a0 50 51 pshl #6, a0 52 assert_sreg 0x400000, a0 53 pshl #-6, a0 54 assert_sreg 0x10000, a0 55 56 pshl #7, a0 57 assert_sreg 0x800000, a0 58 pshl #-7, a0 59 assert_sreg 0x10000, a0 60 61 pshl #8, a0 62 assert_sreg 0x1000000, a0 63 pshl #-8, a0 64 assert_sreg 0x10000, a0 65 66 pshl #9, a0 67 assert_sreg 0x2000000, a0 68 pshl #-9, a0 69 assert_sreg 0x10000, a0 70 71 pshl #10, a0 72 assert_sreg 0x4000000, a0 73 pshl #-10, a0 74 assert_sreg 0x10000, a0 75 76 pshl #11, a0 77 assert_sreg 0x8000000, a0 78 pshl #-11, a0 79 assert_sreg 0x10000, a0 80 81 pshl #12, a0 82 assert_sreg 0x10000000, a0 83 pshl #-12, a0 84 assert_sreg 0x10000, a0 85 86 pshl #13, a0 87 assert_sreg 0x20000000, a0 88 pshl #-13, a0 89 assert_sreg 0x10000, a0 90 91 pshl #14, a0 92 assert_sreg 0x40000000, a0 93 pshl #-14, a0 94 assert_sreg 0x10000, a0 95 96 pshl #15, a0 97 assert_sreg 0x80000000, a0 98 pshl #-15, a0 99 assert_sreg 0x10000, a0 100 101 pshl #16, a0 102 assert_sreg 0x00000000, a0 103 pshl #-16, a0 104 assert_sreg 0x0, a0 105 106 test_grs_a5a5 107 assert_sreg2 0xa5a5a5a5, a1 108 assert_sreg 0xa5a5a5a5, x0 109 assert_sreg 0xa5a5a5a5, x1 110 assert_sreg 0xa5a5a5a5, y0 111 assert_sreg 0xa5a5a5a5, y1 112 assert_sreg2 0xa5a5a5a5, m0 113 assert_sreg2 0xa5a5a5a5, m1 114 115 116 pass 117 exit 0 118 119