1# sh testcase for prnd 2# mach: shdsp 3# as(shdsp): -defsym sim_cpu=1 -dsp 4 5 # FIXME: opcode table ambiguity in ignored bits 4-7. 6 7 .include "testutils.inc" 8 9 start 10 set_grs_a5a5 11 lds r0, a0 12 pcopy a0, a1 13 lds r0, x0 14 lds r0, x1 15 lds r0, y0 16 lds r0, y1 17 pcopy x0, m0 18 pcopy y1, m1 19 20 # prnd(0xa5a5a5a5) = 0xa5a60000 21 prnd x0, x0 22 prnd y0, y0 23 assert_sreg 0xa5a60000, x0 24 assert_sreg 0xa5a60000, y0 25 26 # prnd(1) = 1 27 mov #1, r0 28 shll16 r0 29 lds r0, x0 30 pcopy x0, y0 31 prnd x0, x0 32 prnd y0, y0 33 assert_sreg 0x10000, x0 34 assert_sreg 0x10000, y0 35 36 # prnd(1.4999999) = 1 37 mov #1, r0 38 shll8 r0 39 or #0x7f, r0 40 shll8 r0 41 or #0xff, r0 42 lds r0, x0 43 pcopy x0, y0 44 prnd x0, x0 45 prnd y0, y0 46 assert_sreg 0x10000, x0 47 assert_sreg 0x10000, y0 48 49 # prnd(1.5) = 2 50 mov #1, r0 51 shll8 r0 52 or #0x80, r0 53 shll8 r0 54 lds r0, x0 55 pcopy x0, y0 56 prnd x0, x0 57 prnd y0, y0 58 assert_sreg 0x20000, x0 59 assert_sreg 0x20000, y0 60 61 # dct prnd 62 set_dcfalse 63 dct prnd x0, x1 64 dct prnd y0, y1 65 assert_sreg2 0xa5a5a5a5, x1 66 assert_sreg2 0xa5a5a5a5, y1 67 set_dctrue 68 dct prnd x0, x1 69 dct prnd y0, y1 70 assert_sreg2 0x20000, x1 71 assert_sreg2 0x20000, y1 72 73 # dcf prnd 74 set_dctrue 75 dcf prnd x0, m0 76 dcf prnd y0, m1 77 assert_sreg2 0xa5a5a5a5, m0 78 assert_sreg2 0xa5a5a5a5, m1 79 set_dcfalse 80 dcf prnd x0, m0 81 dcf prnd y0, m1 82 assert_sreg2 0x20000, m0 83 assert_sreg2 0x20000, m1 84 85 set_greg 0xa5a5a5a5, r0 86 test_grs_a5a5 87 assert_sreg 0xa5a5a5a5, a0 88 assert_sreg2 0xa5a5a5a5, a1 89 pass 90 exit 0 91