1# Test that unsigned widening multiplication of 32-bit operands to produce a 2# 64-bit result is simulated correctly, when using 32-bit or F5series hardware 3# multiply functionality. 4# 0xffff fffc * 0x2 = 0x1 ffff fff8 5# mach: msp430 6 7# 32-bit hwmult register addresses 8.set MPY32L, 0x0140 9.set MPY32H, 0x0142 10.set OP2L, 0x0150 11.set OP2H, 0x0152 12.set RES0, 0x0154 13.set RES1, 0x0156 14.set RES2, 0x0158 15.set RES3, 0x015A 16 17# F5series hwmult register addresses 18.set MPY32L_F5, 0x04D0 19.set MPY32H_F5, 0x04D2 20.set OP2L_F5, 0x04E0 21.set OP2H_F5, 0x04E2 22.set RES0_F5, 0x04E4 23.set RES1_F5, 0x04E6 24.set RES2_F5, 0x04E8 25.set RES3_F5, 0x04EA 26 27.include "testutils.inc" 28 29 start 30 31 ; Test 32bit hwmult 32 MOV.W #2, &MPY32L ; Load operand 1 Low into multiplier 33 MOV.W #0, &MPY32H ; Load operand 1 High into multiplier 34 MOV.W #-4, &OP2L ; Load operand 2 Low into multiplier 35 MOV.W #-1, &OP2H ; Load operand 2 High, trigger MPY 36 37 CMP.W #-8, &RES0 { JNE .L5 38 CMP.W #-1, &RES1 { JNE .L5 39 CMP.W #1, &RES2 { JNE .L5 40 CMP.W #0, &RES3 { JNE .L5 41 42 ; Test f5series hwmult 43 MOV.W #2, &MPY32L_F5 44 MOV.W #0, &MPY32H_F5 45 MOV.W #-4, &OP2L_F5 46 MOV.W #-1, &OP2H_F5 47 48 CMP.W #-8, &RES0_F5 { JNE .L5 49 CMP.W #-1, &RES1_F5 { JNE .L5 50 CMP.W #1, &RES2_F5 { JNE .L5 51 CMP.W #0, &RES3_F5 { JEQ .L6 52.L5: 53 fail 54.L6: 55 pass 56