xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/m32r/rte.cgs (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c)
1# m32r testcase for rte
2# mach(): m32r m32rx
3
4	.include "testutils.inc"
5
6	start
7
8	.global rte
9rte:
10
11; Test 1: bbpsw = 0, bpsw = 1, psw = 0
12
13	; bbsm = 0, bie = 0, bbcond = 0
14	mvi_h_gr r4, 0
15	mvtc r4, cr8
16
17	; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
18	mvi_h_gr r4, 0xc100
19	mvtc r4, cr0
20
21	; bbpc = 0
22	mvaddr_h_gr r4, 0
23	mvtc r4, bbpc
24
25	; bpc = ret1
26	mvaddr_h_gr r4, ret1
27	mvtc r4, bpc
28
29	rte
30	fail
31
32ret1:
33	; test bbsm = 0, bbie = 0, bbcond = 0
34	mvfc r4, cr8
35	test_h_gr r4, 0
36
37	; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
38	mvfc r4, cr0
39	test_h_gr r4, 0xc1
40
41	; test bbpc = 0
42	mvfc r4, bbpc
43	test_h_gr r4, 0
44
45	; test bpc = 0
46	mvfc r4, bpc
47	test_h_gr r4, 0
48
49; Test 2: bbpsw = 1, bpsw = 0, psw = 1
50
51	; bbsm = 1, bie = 1, bbcond = 1
52	mvi_h_gr r4, 0xc1
53	mvtc r4, cr8
54
55	; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
56	mvi_h_gr r4, 0xc1
57	mvtc r4, cr0
58
59	; bbpc = 42
60	mvaddr_h_gr r4, 42
61	mvtc r4, bbpc
62
63	; bpc = ret2 + 2
64	mvaddr_h_gr r4, ret2 + 2
65	mvtc r4, bpc
66
67	rte
68	fail
69
70ret2:
71	; test bbsm = 1, bbie = 1, bbcond = 1
72	mvfc r4, cr8
73	test_h_gr r4, 0xc1
74
75	; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
76	mvfc r4, cr0
77	test_h_gr r4, 0xc100
78
79	; test bbpc = 42
80	mvfc r4, bbpc
81	test_h_gr r4, 42
82
83	; test bpc = 42
84	mvfc r4, bpc
85	test_h_gr r4, 42
86
87	pass
88