1# frv testcase for ftule $FCCi_2,$GRi,$GRj 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global ftule 9ftule: 10 and_spr_immed -4081,tbr ; clear tbr.tt 11 set_gr_spr tbr,gr7 12 inc_gr_immed 2112,gr7 ; address of exception handler 13 set_bctrlr_0_0 gr7 ; bctrlr 0,0 14 15 set_spr_immed 128,lcr 16 set_gr_immed 0,gr7 17 set_gr_immed 4,gr8 18 19 set_spr_addr bad,lr 20 set_fcc 0x0 0 21 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 22 23 set_psr_et 1 24 set_spr_addr ok1,lr 25 set_fcc 0x1 0 26 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 27 fail 28ok1: 29 set_spr_addr bad,lr 30 set_fcc 0x2 0 31 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 32 33 set_psr_et 1 34 set_spr_addr ok3,lr 35 set_fcc 0x3 0 36 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 37 fail 38ok3: 39 set_psr_et 1 40 set_spr_addr ok4,lr 41 set_fcc 0x4 0 42 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 43 fail 44ok4: 45 set_psr_et 1 46 set_spr_addr ok5,lr 47 set_fcc 0x5 0 48 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 49 fail 50ok5: 51 set_psr_et 1 52 set_spr_addr ok6,lr 53 set_fcc 0x6 0 54 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 55 fail 56ok6: 57 set_psr_et 1 58 set_spr_addr ok7,lr 59 set_fcc 0x7 0 60 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 61 fail 62ok7: 63 set_psr_et 1 64 set_spr_addr ok8,lr 65 set_fcc 0x8 0 66 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 67 fail 68ok8: 69 set_psr_et 1 70 set_spr_addr ok9,lr 71 set_fcc 0x9 0 72 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 73 fail 74ok9: 75 set_psr_et 1 76 set_spr_addr oka,lr 77 set_fcc 0xa 0 78 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 79 fail 80oka: 81 set_psr_et 1 82 set_spr_addr okb,lr 83 set_fcc 0xb 0 84 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 85 fail 86okb: 87 set_psr_et 1 88 set_spr_addr okc,lr 89 set_fcc 0xc 0 90 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 91 fail 92okc: 93 set_psr_et 1 94 set_spr_addr okd,lr 95 set_fcc 0xd 0 96 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 97 fail 98okd: 99 set_psr_et 1 100 set_spr_addr oke,lr 101 set_fcc 0xe 0 102 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 103 fail 104oke: 105 set_psr_et 1 106 set_spr_addr okf,lr 107 set_fcc 0xf 0 108 ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 109 fail 110okf: 111 pass 112bad: 113 fail 114