xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/c_mmr_interr_ctl.s (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c) 
1# Blackfin testcase for the CEC
2# mach: bfin
3# sim: --environment operating
4
5	.include "testutils.inc"
6
7	start
8
9	INIT_R_REGS 0;
10	INIT_P_REGS 0;
11	INIT_I_REGS 0;
12	INIT_M_REGS 0;
13	INIT_L_REGS 0;
14	INIT_B_REGS 0;
15
16	CLI R1;               // inhibit events during MMR writes
17
18	loadsym sp, USTACK;   // setup the user stack pointer
19	usp = sp;                  // and frame pointer
20
21	loadsym sp, KSTACK;   // setup the stack pointer
22	fp = sp;                  // and frame pointer
23
24	imm32 p0, 0xFFE02000;
25	loadsym r0, EHANDLE;  // Emulation Handler (Int0)
26	[p0++] = r0;
27
28	loadsym r0, RHANDLE;  // Reset Handler (Int1)
29	[p0++] = r0;
30
31	loadsym r0, NHANDLE;  // NMI Handler (Int2)
32	[p0++] = r0;
33
34	loadsym r0, XHANDLE;  // Exception Handler (Int3)
35	[p0++] = r0;
36
37	[p0++] = r0;          // EVT4 not used global Interr Enable (INT4)
38
39	loadsym r0, HWHANDLE; // HW Error Handler (Int5)
40	[p0++] = r0;
41
42	loadsym r0, THANDLE;  // Timer Handler (Int6)
43	[p0++] = r0;
44
45	loadsym r0, I7HANDLE; // IVG7 Handler
46	[p0++] = r0;
47
48	loadsym r0, I8HANDLE; // IVG8 Handler
49	[p0++] = r0;
50
51	loadsym r0, I9HANDLE; // IVG9 Handler
52	[p0++] = r0;
53
54	loadsym r0, I10HANDLE;// IVG10 Handler
55	[p0++] = r0;
56
57	loadsym r0, I11HANDLE;// IVG11 Handler
58	[p0++] = r0;
59
60	loadsym r0, I12HANDLE;// IVG12 Handler
61	[p0++] = r0;
62
63	loadsym r0, I13HANDLE;// IVG13 Handler
64	[p0++] = r0;
65
66	loadsym r0, I14HANDLE;// IVG14 Handler
67	[p0++] = r0;
68
69	loadsym r0, I15HANDLE;// IVG15 Handler
70	[p0++] = r0;
71
72	imm32 p0, 0xFFE02100  // EVT_OVERRIDE
73	r0 = 0;
74	[p0++] = r0;
75
76	r1 = -1;     // Change this to mask interrupts (*)
77	csync;       // wait for MMR writes to finish
78	sti r1;      // sync and reenable events (implicit write to IMASK)
79
80	imm32 p0, 0xFFE02104;
81	r0   = [p0];
82	// ckeck that sti allows the lower 5 bits of imask to be written
83	CHECKREG r0, 0xffff;
84
85DUMMY:
86
87	r0 = 0 (z);
88
89	LT0 = r0;       // set loop counters to something deterministic
90	LB0 = r0;
91	LC0 = r0;
92	LT1 = r0;
93	LB1 = r0;
94	LC1 = r0;
95
96	ASTAT = r0;     // reset other internal regs
97	SYSCFG = r0;
98	RETS = r0;      // prevent X's breaking LINK instruction
99
100// The following code sets up the test for running in USER mode
101
102	loadsym r0, STARTUSER;// One gets to user mode by doing a
103	                    // ReturnFromInterrupt (RTI)
104	RETI = r0;      // We need to load the return address
105
106// Comment the following line for a USER Mode test
107
108	JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
109
110	RTI;
111
112STARTSUP:
113	loadsym p1, BEGIN;
114
115	imm32 p0, (0xFFE02000 + 4 * 15);
116
117	CLI R1;    // inhibit events during write to MMR
118	[p0] = p1;   // IVG15 (General) handler (Int 15) load with start
119	csync;       // wait for it
120	sti r1;      // reenable events with proper imask
121
122	RAISE 15;       // after we RTI, INT 15 should be taken
123
124	RTI;
125
126//
127// The Main Program
128//
129STARTUSER:
130	LINK 0;     // change for how much stack frame space you need.
131
132	JUMP BEGIN;
133
134// *********************************************************************
135
136BEGIN:
137
138	            // COMMENT the following line for USER MODE tests
139	[--sp] = RETI;  // enable interrupts in supervisor mode
140
141	            // **** YOUR CODE GOES HERE ****
142// EVTx
143	// wrt-rd  EVT0: 0 bits, rw=0   = 0xFFE02000
144	imm32 p0, 0xFFE02000;
145	imm32 r0, 0x00000000
146	[p0] = r0;
147
148	// wrt-rd EVT1: 32 bits, rw=0   = 0xFFE02004
149	imm32 p0, 0xFFE02004;
150	imm32 r0, 0x00000000
151	[p0] = r0;
152
153	// wrt-rd     EVT2              = 0xFFE02008
154	imm32 p0, 0xFFE02008
155	imm32 r0, 0xE1DE5D1C
156	[p0] = r0;
157
158	// wrt-rd     EVT3              = 0xFFE0200C
159	imm32 p0, 0xFFE0200C
160	imm32 r0, 0x9CC20332
161	[p0] = r0;
162
163	// wrt-rd     EVT4              = 0xFFE02010
164	imm32 p0, 0xFFE02010
165	imm32 r0, 0x00000000
166	[p0] = r0;
167
168	// wrt-rd     EVT5              = 0xFFE02014
169	imm32 p0, 0xFFE02014
170	imm32 r0, 0x55552345
171	[p0] = r0;
172
173	// wrt-rd     EVT6              = 0xFFE02018
174	imm32 p0, 0xFFE02018
175	imm32 r0, 0x66663456
176	[p0] = r0;
177
178	// wrt-rd     EVT7              = 0xFFE0201C
179	imm32 p0, 0xFFE0201C
180	imm32 r0, 0x77774567
181	[p0] = r0;
182
183	// wrt-rd     EVT8              = 0xFFE02020
184	imm32 p0, 0xFFE02020
185	imm32 r0, 0x88885678
186	[p0] = r0;
187
188	// wrt-rd     EVT9              = 0xFFE02024
189	imm32 p0, 0xFFE02024
190	imm32 r0, 0x99996789
191	[p0] = r0;
192
193	// wrt-rd     EVT10             = 0xFFE02028
194	imm32 p0, 0xFFE02028
195	imm32 r0, 0xaaaa1234
196	[p0] = r0;
197
198	// wrt-rd     EVT11             = 0xFFE0202C
199	imm32 p0, 0xFFE0202C
200	imm32 r0, 0xBBBBABC6
201	[p0] = r0;
202
203	// wrt-rd     EVT12             = 0xFFE02030
204	imm32 p0, 0xFFE02030
205	imm32 r0, 0xCCCCABC6
206	[p0] = r0;
207
208	// wrt-rd     EVT13             = 0xFFE02034
209	imm32 p0, 0xFFE02034
210	imm32 r0, 0xDDDDABC6
211	[p0] = r0;
212
213	// wrt-rd     EVT14             = 0xFFE02038
214	imm32 p0, 0xFFE02038
215	imm32 r0, 0xEEEEABC6
216	[p0] = r0;
217
218	// wrt-rd     EVT15             = 0xFFE0203C
219	imm32 p0, 0xFFE0203C
220	imm32 r0, 0xFFFFABC6
221	[p0] = r0;
222
223	// wrt-rd  EVT_OVERRIDE:9 bits  = 0xFFE02100
224	imm32 p0, 0xFFE02100
225	imm32 r0, 0x000001ff
226	[p0] = r0;
227
228	// wrt-rd  IMASK: 16 bits       = 0xFFE02104
229	imm32 p0, 0xFFE02104
230	imm32 r0, 0x00000fff
231	[p0] = r0;
232
233	// wrt-rd  IPEND: 16 bits, rw=0 = 0xFFE02108
234	imm32 p0, 0xFFE02108
235	imm32 r0, 0x00000000
236	//[p0] = r0;
237	raise 12;
238	raise 13;
239
240	// wrt-rd  ILAT: 16 bits, rw=0  = 0xFFE0210C
241	imm32 p0, 0xFFE0210C
242	imm32 r0, 0x00000000
243	//[p0] = r0;
244	csync;
245
246	// *** read ops
247	imm32 p0, 0xFFE02000
248	r0   = [p0];
249	CHECKREG r0, 0;
250
251	imm32 p0, 0xFFE02004
252	r1   = [p0];
253	CHECKREG r1, 0;
254
255	imm32 p0, 0xFFE02008
256	r2   = [p0];
257	CHECKREG r2, 0xE1DE5D1C;
258
259	imm32 p0, 0xFFE0200C
260	r3   = [p0];
261	CHECKREG r3, 0x9CC20332;
262
263	imm32 p0, 0xFFE02014
264	r4   = [p0];
265	imm32 p0, 0xFFE02018
266	r5   = [p0];
267	imm32 p0, 0xFFE0201C
268	r6   = [p0];
269	imm32 p0, 0xFFE02020	/* EVT8 */
270	r7   = [p0];
271CHECKREG r0, 0x00000000;
272//CHECKREG(r1, 0x00000000);   /// mismatch = 00
273CHECKREG r2, 0xE1DE5D1C;
274CHECKREG r3, 0x9CC20332;
275CHECKREG r4, 0x55552345;
276CHECKREG r5, 0x66663456;
277CHECKREG r6, 0x77774567;
278CHECKREG r7, 0x88885678;
279
280	imm32 p0, 0xFFE02024	/* EVT9 */
281	r0   = [p0];
282	imm32 p0, 0xFFE02028	/* EVT10 */
283	r1   = [p0];
284	imm32 p0, 0xFFE0202C	/* EVT11 */
285	r2   = [p0];
286	imm32 p0, 0xFFE02030	/* EVT12 */
287	r3   = [p0];
288	imm32 p0, 0xFFE02034	/* EVT13 */
289	r4   = [p0];
290	imm32 p0, 0xFFE02038	/* EVT14 */
291	r5   = [p0];
292	imm32 p0, 0xFFE0203C	/* EVT15 */
293	r6   = [p0];
294CHECKREG r0, 0x99996789;
295CHECKREG r1, 0xaaaa1234;
296CHECKREG r2, 0xBBBBABC6;
297CHECKREG r3, 0xCCCCABC6;
298CHECKREG r4, 0xDDDDABC6;
299CHECKREG r5, 0xEEEEABC6;
300CHECKREG r6, 0xFFFFABC6;
301
302	imm32 p0, 0xFFE02100	/* EVT_OVERRIDE */
303	r0   = [p0];
304	imm32 p0, 0xFFE02104	/* IMASK */
305	r1   = [p0];
306	imm32 p0, 0xFFE02108	/* IPEND */
307	r2   = [p0];
308	imm32 p0, 0xFFE0210C	/* ILAT */
309	r3   = [p0];
310CHECKREG r0, 0x000001ff;
311CHECKREG r1, 0x00000fff;	/* XXX: original had 0xfe0 ??  */
312CHECKREG r2, 0x00008000;
313CHECKREG r3, 0x00003000;
314
315	dbg_pass;
316
317// *********************************************************************
318
319//
320// Handlers for Events
321//
322
323EHANDLE:            // Emulation Handler 0
324	RTE;
325
326RHANDLE:            // Reset Handler 1
327	RTI;
328
329NHANDLE:            // NMI Handler 2
330	r0 = 2;
331	RTN;
332
333XHANDLE:            // Exception Handler 3
334
335	RTX;
336
337HWHANDLE:           // HW Error Handler 5
338	r2 = 5;
339	RTI;
340
341THANDLE:            // Timer Handler 6
342	r3 = 6;
343	RTI;
344
345I7HANDLE:           // IVG 7 Handler
346	r4 = 7;
347	RTI;
348
349I8HANDLE:           // IVG 8 Handler
350	r5 = 8;
351	RTI;
352
353I9HANDLE:           // IVG 9 Handler
354	r6 = 9;
355	RTI;
356
357I10HANDLE:          // IVG 10 Handler
358	r7 = 10;
359	RTI;
360
361I11HANDLE:          // IVG 11 Handler
362	r0 = 11;
363	RTI;
364
365I12HANDLE:          // IVG 12 Handler
366	r1 = 12;
367	RTI;
368
369I13HANDLE:          // IVG 13 Handler
370	r2 = 13;
371	RTI;
372
373I14HANDLE:          // IVG 14 Handler
374	r3 = 14;
375	RTI;
376
377I15HANDLE:          // IVG 15 Handler
378	r4 = 15;
379	RTI;
380
381	nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
382
383//
384// Data Segment
385//
386
387.data
388// Stack Segments (Both Kernel and User)
389
390.rep 0x10
391.byte 0
392.endr
393KSTACK:
394
395.rep 0x10
396.byte 0
397.endr
398USTACK:
399